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Ken S. Stevens: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Peter A. Beerel, Ken S. Stevens, Hoshik Kim
    Relative Timing Based Verification of Timed Circuits and Systems. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:115-0 [Conf]
  2. Wei-Chun Chou, Peter A. Beerel, Ran Ginosar, Rakefet Kol, Chris J. Myers, Shai Rotem, Ken S. Stevens, Kenneth Y. Yun
    Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:80-0 [Conf]
  3. Marly Roncken, Ken S. Stevens, Rajesh Pendurkar, Shai Rotem, Parimal Pal Chaudhuri
    CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:62-72 [Conf]
  4. Shai Rotem, Ken S. Stevens, Charles Dike, Marly Roncken, Boris Agapiev, Ran Ginosar, Rakefet Kol, Peter A. Beerel, Chris J. Myers, Kenneth Y. Yun
    RAPPID: An Asynchronous Instruction Length Decoder. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:60-70 [Conf]
  5. Ken S. Stevens, Shai Rotem, Ran Ginosar
    Relative Timing. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:208-218 [Conf]
  6. Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy
    Fsimac: a fault simulator for asynchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:114-119 [Conf]
  7. Ken S. Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, Marly Roncken
    CAD Directions for High Performance Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:116-121 [Conf]
  8. Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Ken S. Stevens
    Synthesis of asynchronous control circuits with automatically generated relative timing assumptions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:324-331 [Conf]
  9. Ken S. Stevens, Sandeep K. Shukla, Montek Singh, Jean-Pierre Talpin
    Preface. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2006, v:146, n:2, pp:1-3 [Journal]
  10. Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Alex Kondratyev, Luciano Lavagno, Ken S. Stevens, Alexander Taubin, Alexandre Yakovlev
    Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:109-130 [Journal]
  11. Ken S. Stevens, Ran Ginosar, Shai Rotem
    Relative timing [asynchronous design]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:129-140 [Journal]

  12. Guest Editors' Introduction: GALS Design and Validation. [Citation Graph (, )][DBLP]

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