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Publications of Author

1. Edith Beigné, Fabien Clermidy, Pascal Vivet, Alain Clouard, Marc Renaudin
   An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2005, pp:54-63 [Conf]
   
2. Edith Beigné, Pascal Vivet
   Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2006, pp:172-183 [Conf]
   
3. Marc Renaudin, Pascal Vivet, Frédéric Robin
   ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor. [Citation Graph (0, 0)][DBLP]
   ASYNC, 1998, pp:22-31 [Conf]
   
4. Marc Renaudin, Pascal Vivet, Frédéric Robin
   A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation. [Citation Graph (0, 0)][DBLP]
   ASYNC, 1999, pp:135-144 [Conf]
   
5. Gwen Salaün, Wendelin Serwe, Yvain Thonnart, Pascal Vivet
   Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2007, pp:73-82 [Conf]
   
6. Sylvain Miermont, Pascal Vivet, Marc Renaudin
   A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2007, pp:556-565 [Conf]
   
7. Cedric Koch-Hofer, Marc Renaudin, Yvain Thonnart, Pascal Vivet
   ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC. [Citation Graph (0, 0)][DBLP]
   NOCS, 2007, pp:295-306 [Conf]
   
8. 
   A fully-asynchronous low-power framework for GALS NoC integration. [Citation Graph (, )][DBLP]
   
   
9. 
   A Transaction Level Modeling of Network-on-Chip Architecture for Energy Estimation. [Citation Graph (, )][DBLP]
   
   
10. 
    Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC. [Citation Graph (, )][DBLP]
    
    
11. 
    A Communication and configuration controller for NoC based reconfigurable data flow architecture. [Citation Graph (, )][DBLP]
    
    
12. 
    Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture. [Citation Graph (, )][DBLP]
    
    
13. 
    Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook. [Citation Graph (, )][DBLP]