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Montek Singh :
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Justin Hensley , Anselmo Lastra , Montek Singh A Scalable Counterflow-Pipelined Asynchronous Radix-4 Booth Multiplier. [Citation Graph (0, 0)][DBLP ] ASYNC, 2005, pp:128-137 [Conf ] José A. Tierno , Sergey Rylov , Alexander Rylyakov , Montek Singh , Steven M. Nowick An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz. [Citation Graph (0, 0)][DBLP ] ASYNC, 2002, pp:84-0 [Conf ] Montek Singh , Steven M. Nowick High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths. [Citation Graph (0, 0)][DBLP ] ASYNC, 2000, pp:198-0 [Conf ] Gennette Gill , Ankur Agiwal , Montek Singh , Feng Shi , Yiorgos Makris Low-Overhead Testing of Delay Faults in High-Speed Asynchronous Pipelines. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:46-56 [Conf ] Recep O. Ozdag , Peter A. Beerel , Montek Singh , Steven M. Nowick High-Speed Non-Linear Asynchronous Pipelines. [Citation Graph (0, 0)][DBLP ] DATE, 2002, pp:1000-1007 [Conf ] Montek Singh , Michael Theobald Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures. [Citation Graph (0, 0)][DBLP ] DATE, 2004, pp:1008-1013 [Conf ] Ankur Agiwal , Montek Singh An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:1006-1013 [Conf ] Montek Singh Memory access optimization of dynamic binary translation for reconfigurable architectures. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:1014-1020 [Conf ] Gennette Gill , John Hansen , Montek Singh Loop pipelining for high-throughput stream computation using self-timed rings. [Citation Graph (0, 0)][DBLP ] ICCAD, 2006, pp:289-296 [Conf ] Manoj Ampalam , Montek Singh Counterflow pipelining: architectural support for preemption in asynchronous systems using anti-tokens. [Citation Graph (0, 0)][DBLP ] ICCAD, 2006, pp:611-618 [Conf ] Justin Hensley , Anselmo Lastra , Montek Singh An Area- and Energy-Efficient Asynchronous Booth Multiplier for Mobile Devices. [Citation Graph (0, 0)][DBLP ] ICCD, 2004, pp:18-25 [Conf ] Montek Singh , Steven M. Nowick MOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines. [Citation Graph (0, 0)][DBLP ] ICCD, 2001, pp:9-17 [Conf ] Montek Singh , Steven M. Nowick Synthesis-for-Initializability of Asynchronous Sequential Machines. [Citation Graph (0, 0)][DBLP ] ITC, 1996, pp:232-241 [Conf ] Montek Singh , Steven M. Nowick Synthesis for Logical Initializability of Synchronous Finite State Machines. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1997, pp:76-81 [Conf ] Ankur Agiwal , Montek Singh Multi-Clock Latency-Insensitive Architecture and Wrapper Synthesis. [Citation Graph (0, 0)][DBLP ] Electr. Notes Theor. Comput. Sci., 2006, v:146, n:2, pp:5-28 [Journal ] Ken S. Stevens , Sandeep K. Shukla , Montek Singh , Jean-Pierre Talpin Preface. [Citation Graph (0, 0)][DBLP ] Electr. Notes Theor. Comput. Sci., 2006, v:146, n:2, pp:1-3 [Journal ] Montek Singh , Amitabha Chatterjee , Santanu Chaudhury Matching structural shape descriptions using genetic algorithms. [Citation Graph (0, 0)][DBLP ] Pattern Recognition, 1997, v:30, n:9, pp:1451-1462 [Journal ] Justin Hensley , Montek Singh , Anselmo Lastra A fast, energy-efficient z-comparator. [Citation Graph (0, 0)][DBLP ] Graphics Hardware, 2005, pp:41-44 [Conf ] Justin Hensley , Thorsten Scheuermann , Greg Coombe , Montek Singh , Anselmo Lastra Fast Summed-Area Table Generation and its Applications. [Citation Graph (0, 0)][DBLP ] Comput. Graph. Forum, 2005, v:24, n:3, pp:547-555 [Journal ] Montek Singh , Steven M. Nowick The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1256-1269 [Journal ] Montek Singh , Steven M. Nowick The Design of High-Performance Dynamic Asynchronous Pipelines: High-Capacity Style. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1270-1283 [Journal ] Montek Singh , Steven M. Nowick MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:684-698 [Journal ] Montek Singh , Steven M. Nowick Synthesis for logical initializability of synchronous finite-state machines. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:542-557 [Journal ] Performance estimation and slack matching for pipelined asynchronous architectures with choice. [Citation Graph (, )][DBLP ] Energy-precision tradeoffs in mobile Graphics Processing Units. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.305secs