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Publications of Author

1. 
   QoS for Networked Heterogeneous Real-Time Embedded Systems. [Citation Graph (, )][DBLP]
   
   
2. 
   Energy-aware register file re-partitioning for clustered VLIW architectures. [Citation Graph (, )][DBLP]
   
   
3. 
   Computation and data transfer co-scheduling for interconnection bus minimization. [Citation Graph (, )][DBLP]
   
   
4. 
   Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation. [Citation Graph (, )][DBLP]
   
   
5. 
   Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints. [Citation Graph (, )][DBLP]
   
   
6. 
   Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory. [Citation Graph (, )][DBLP]
   
   
7. 
   Write activity reduction on flash main memory via smart victim cache. [Citation Graph (, )][DBLP]
   
   
8. 
   A Formal Specification and Verification Framework for Designing and Verifying Reliable and Dependable Software for Computerized Numerical Control (CNC) Systems. [Citation Graph (, )][DBLP]
   
   
9. 
   Joint Sleep Scheduling and Mode Assignment in Wireless Cyber-Physical Systems. [Citation Graph (, )][DBLP]
   
   
10. 
    Minimizing Leakage Energy with Modulo Scheduling for VLIW DSP Processors. [Citation Graph (, )][DBLP]
    
    
11. 
    Analysis and approximation for bank selection instruction minimization on partitioned memory architecture. [Citation Graph (, )][DBLP]
    
    
12. 
    Minimizing WCET for Real-Time Embedded Systems via Static Instruction Cache Locking. [Citation Graph (, )][DBLP]
    
    
13. 
    Energy Efficient Operating Mode Assignment for Real-Time Tasks in Wireless Embedded Systems. [Citation Graph (, )][DBLP]
    
    
14. 
    Instruction Cache Locking for Real-Time Embedded Systems with Multi-tasks. [Citation Graph (, )][DBLP]
    
    
15. 
    Minimizing Transferred Data for Code Update on Wireless Sensor Network. [Citation Graph (, )][DBLP]
    
    
16. 
    Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks. [Citation Graph (, )][DBLP]