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Jens Sparsø: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tobias Bjerregaard, Jens Sparsø
    A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2005, pp:34-43 [Conf]
  2. Kåre T. Christensen, Peter Jensen, Peter Korger, Jens Sparsø
    The Design of an Asynchronous TinyRISCTM TR4101 Microprocessor Core. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:108-0 [Conf]
  3. Tobias Bjerregaard, Jens Sparsø
    A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1226-1231 [Conf]
  4. Shankar Mahadevan, Federico Angiolini, Michael Storgaard, Rasmus Grøndahl Olsen, Jens Sparsø, Jan Madsen
    A Network Traffic Generator Model for Fast Network-on-Chip Simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:780-785 [Conf]
  5. S. F. Nielsen, Jens Sparsø, Jan Madsen
    Towards Behavioral Synthesis of Asynchronous Circuits - An Implementation Template Targeting Syntax Directed Compilation. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:298-305 [Conf]
  6. Tobias Bjerregaard, Jens Sparsø
    Packetizing OCP Transactions in the MANGO Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:657-664 [Conf]
  7. Mikkel Bystrup Stensgaard, Tobias Bjerregaard, Jens Sparsø, Johnny Halkjær Pedersen
    A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:641-648 [Conf]
  8. Jens Sparsø, Christian D. Nielsen, Lars S. Nielsen, Jørgen Staunstrup
    Design of Self-timed Multipliers: A Comparison. [Citation Graph (0, 0)][DBLP]
    Asynchronous Design Methodologies, 1993, pp:165-179 [Conf]
  9. Vojin G. Oklobdzija, Jens Sparsø
    Future directions in clocking multi-ghz systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:219- [Conf]
  10. Tobias Bjerregaard, Shankar Mahadevan, Jens Sparsø
    A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:301-310 [Conf]
  11. Jens Sparsø, Steen Pedersen, Erik Paaske
    Design of a Fully Parallel Viterbi Decoder. [Citation Graph (0, 0)][DBLP]
    VLSI, 1991, pp:29-38 [Conf]
  12. Tobias Bjerregaard, Mikkel Bystrup Stensgaard, Jens Sparsø
    A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:648-653 [Conf]
  13. Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen
    A Traffic Injection Methodology with Support for System-Level Synchronization. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:145-161 [Conf]
  14. Lars S. Nielsen, C. Niessen, Jens Sparsø, K. van Berkel
    Low-power operation using self-timed circuits and adaptive scaling of the supply voltage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:391-397 [Journal]

  15. Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip. [Citation Graph (, )][DBLP]


  16. ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology. [Citation Graph (, )][DBLP]


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