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Prabhakar Kudva: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hans M. Jacobson, Erik Brunvand, Ganesh Gopalakrishnan, Prabhakar Kudva
    High-Level Asynchronous System Design Using the ACK Framework. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:93-103 [Conf]
  2. Hans M. Jacobson, Prabhakar Kudva, Pradip Bose, Peter W. Cook, Stanley Schuster
    Synchronous Interlocked Pipelines. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:3-12 [Conf]
  3. Prabhat Jain, Prabhakar Kudva, Ganesh Gopalakrishnan
    Towards a Verification Technique for Large Synchronous Circuits. [Citation Graph (0, 0)][DBLP]
    CAV, 1992, pp:109-122 [Conf]
  4. Yiu-Hing Chan, Prabhakar Kudva, Lisa B. Lacey, Gregory A. Northrop, Thomas E. Rosser
    Physical synthesis methodology for high performance microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:696-701 [Conf]
  5. Victor N. Kravets, Prabhakar Kudva
    Implicit enumeration of structural changes in circuit optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:438-441 [Conf]
  6. Prabhakar Kudva, Ganesh Gopalakrishnan, Hans M. Jacobson
    A Technique for Synthesizing Distributed Burst-mode Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:67-70 [Conf]
  7. Prabhakar Kudva, Ganesh Gopalakrishnan, Hans M. Jacobson, Steven M. Nowick
    Synthesis for Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:77-82 [Conf]
  8. Wilm E. Donath, Prabhakar Kudva, Leon Stok, Paul Villarrubia, Lakshmi N. Reddy, Andrew Sullivan, Kanad Chakraborty
    Transformational Placement and Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:194-201 [Conf]
  9. Frederik Beeftink, Prabhakar Kudva, David S. Kung, Leon Stok
    Gate-size selection for standard cell libraries. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:545-550 [Conf]
  10. Prabhakar Kudva, Andrew Sullivan, William E. Dougherty
    Metrics for structural logic synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:551-556 [Conf]
  11. Wilm E. Donath, Prabhakar Kudva, Lakshmi N. Reddy
    Performance Driven Optimization of Network Length in Physical Placement. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:258-265 [Conf]
  12. Ganesh Gopalakrishnan, Prabhakar Kudva, Erik Brunvand
    Peephole Optimization of Asynchronous Macromodule Networks. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:442-446 [Conf]
  13. Prabhakar Kudva, Ganesh Gopalakrishnan, Erik Brunvand, Venkatesh Akella
    Performance Analysis and Optimization of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:221-224 [Conf]
  14. José A. Tierno, Prabhakar Kudva
    Asynchronous Transpose-Matrix Architectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:423-428 [Conf]
  15. W. Chen, Wei Hwang, P. Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi
    Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:263-266 [Conf]
  16. Prabhakar Kudva, Andrew Sullivan, William E. Dougherty
    Metrics for Structural Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:1-6 [Conf]
  17. Pradip Bose, David Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas
    Early-Stage Definition of LPX: A Low Power Issue-Execute Processor. [Citation Graph (0, 0)][DBLP]
    PACS, 2002, pp:1-17 [Conf]
  18. Victor N. Kravets, Prabhakar Kudva
    Understanding metrics in logic synthesis for routability enhancement. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:3-5 [Conf]
  19. Frederik Beeftink, Prabhakar Kudva, David S. Kung, Ruchir Puri, Leon Stok
    Combinatorial cell design for CMOS libraries. [Citation Graph (0, 0)][DBLP]
    Integration, 2000, v:29, n:1, pp:67-93 [Journal]
  20. David Brooks, Pradip Bose, Stanley Schuster, Hans M. Jacobson, Prabhakar Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor V. Zyuban, Manish Gupta, Peter W. Cook
    Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2000, v:20, n:6, pp:26-44 [Journal]
  21. Prabhakar Kudva, Andrew Sullivan, William E. Dougherty
    Measurements for structural logic synthesis optimizations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:665-674 [Journal]
  22. Ganesh Gopalakrishnan, Prabhakar Kudva, Erik Brunvand
    Peephole optimization of asynchronous macromodule networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:30-37 [Journal]

  23. Statistical Fault Injection. [Citation Graph (, )][DBLP]

  24. Power-efficient, reliable microprocessor architectures: modeling and design methods. [Citation Graph (, )][DBLP]

  25. Reliability Challenges and System Performance at the Architecture Level. [Citation Graph (, )][DBLP]

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