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Pradip Bose: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hans M. Jacobson, Prabhakar Kudva, Pradip Bose, Peter W. Cook, Stanley Schuster
    Synchronous Interlocked Pipelines. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:3-12 [Conf]
  2. Pradip Bose
    Parallel Simulation and Test of VLSI Array Logic. [Citation Graph (0, 0)][DBLP]
    AWOC, 1988, pp:301-311 [Conf]
  3. Pradip Bose
    Ensuring Dependable Processor Performance: An Experience Report on Pre-Silicon Performance Validation. [Citation Graph (0, 0)][DBLP]
    DSN, 2001, pp:481-486 [Conf]
  4. Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers
    SoftArch: An Architecture Level Tool for Modeling and Analyzing Soft Errors. [Citation Graph (0, 0)][DBLP]
    DSN, 2005, pp:496-505 [Conf]
  5. Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers
    The Impact of Technology Scaling on Lifetime Reliability. [Citation Graph (0, 0)][DBLP]
    DSN, 2004, pp:177-0 [Conf]
  6. Pradip Bose
    Optimal Code Generation for Expressions on Super Scalar Machines. [Citation Graph (0, 0)][DBLP]
    FJCC, 1986, pp:372-379 [Conf]
  7. Pradip Bose
    Architectural Timing Verification and Test for Super Scalar Processors. [Citation Graph (0, 0)][DBLP]
    FTCS, 1994, pp:256-265 [Conf]
  8. Alper Buyuktosunoglu, David H. Albonesi, Stanley Schuster, David Brooks, Pradip Bose, Peter W. Cook
    A circuit level implementation of an adaptive issue queue for power-aware microprocessors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:73-78 [Conf]
  9. Vijay S. Iyengar, Louise Trevillyan, Pradip Bose
    Representative Traces for Processor Models with Infinite Cache. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:62-72 [Conf]
  10. Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Rick Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler
    Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:238-242 [Conf]
  11. Pradip Bose
    Early Performance Estimation of Super Scalar Machine Models. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:388-392 [Conf]
  12. Pradip Bose, David LaPotin, Gopalakrishnan Vijayan, SungHo Kim
    Workload-Driven Floorplanning for MIPS Optimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:387-391 [Conf]
  13. S. Surya, Pradip Bose, Jacob A. Abraham
    Architectural Performance Verification: PowerPCTM Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:344-347 [Conf]
  14. Pradip Bose
    Heuristic Rule-Based Program Transformations for Enhanced Vectorization. [Citation Graph (0, 0)][DBLP]
    ICPP (2), 1988, pp:63-66 [Conf]
  15. Pradip Bose
    Interactive program improvement via EAVE: an expert adviser for vectorization. [Citation Graph (0, 0)][DBLP]
    ICS, 1988, pp:119-130 [Conf]
  16. Anthony-Trung Nguyen, Pradip Bose, Kattamuri Ekanadham, Ashwini K. Nanda, Maged M. Michael
    Accuracy and Speedup of Parallel Trace-Driven Architectural Simulation. [Citation Graph (0, 0)][DBLP]
    IPPS, 1997, pp:39-44 [Conf]
  17. Pradip Bose, Edward S. Davidson
    Design of Instruction Set Architectures for Support of High-Level Languages . [Citation Graph (0, 0)][DBLP]
    ISCA, 1984, pp:198-206 [Conf]
  18. Alper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose
    Energy Efficient Co-Adaptive Instruction Fetch and Issue. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:147-156 [Conf]
  19. Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers
    The Case for Lifetime Reliability-Aware Microprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:276-287 [Conf]
  20. Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers
    Exploiting Structural Duplication for Lifetime Reliability Enhancement. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:520-531 [Conf]
  21. Alper Buyuktosunoglu, David H. Albonesi, Pradip Bose, Peter W. Cook, Stanley Schuster
    Tradeoffs in power-efficient issue queue design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:184-189 [Conf]
  22. Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose
    Microarchitectural techniques for power gating of execution units. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:32-37 [Conf]
  23. Tejas Karkhanis, James E. Smith, Pradip Bose
    Saving energy with just in time instruction delivery. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:178-183 [Conf]
  24. Yingmin Li, David Brooks, Zhigang Hu, Kevin Skadron, Pradip Bose
    Understanding the energy efficiency of simultaneous multithreading. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:44-49 [Conf]
  25. Viji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose, Victor V. Zyuban, Philip N. Strenski, Philip G. Emma
    Optimizing pipelines for power and performance. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:333-344 [Conf]
  26. Canturk Isci, Alper Buyuktosunoglu, Chen-Yong Cher, Pradip Bose, Margaret Martonosi
    An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:347-358 [Conf]
  27. Pradip Bose, David Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas
    Early-Stage Definition of LPX: A Low Power Issue-Execute Processor. [Citation Graph (0, 0)][DBLP]
    PACS, 2002, pp:1-17 [Conf]
  28. David Brooks, Margaret Martonosi, John-David Wellman, Pradip Bose
    Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor. [Citation Graph (0, 0)][DBLP]
    PACS, 2000, pp:126-136 [Conf]
  29. Alper Buyuktosunoglu, Stanley Schuster, David Brooks, Pradip Bose, Peter W. Cook, David H. Albonesi
    An Adaptive Issue Queue for Reduced Power at High Performance. [Citation Graph (0, 0)][DBLP]
    PACS, 2000, pp:25-39 [Conf]
  30. Pradip Bose
    Performance Evaluation and Validation of Microprocessors. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1999, pp:226-227 [Conf]
  31. Pradip Bose
    Power-Aware, Reliable Microprocessor Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:3-0 [Conf]
  32. Pradip Bose, Jacob A. Abraham
    Performance and Functional Verification of Microprocessors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:58-63 [Conf]
  33. Pradip Bose, John-David Wellman
    MIPS-Driven Early Design and Analysis of VLSI CPU Chips. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:256-259 [Conf]
  34. Hendrik F. Hamann, Alan J. Weger, James Lacey, Zhigang Hu, Pradip Bose, Erwin Cohen, Jamil A. Wakil
    Temperature-limited microprocessors: Measurements and design implications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:427-432 [Conf]
  35. Pradip Bose
    Performance Test Case Generation for Microprocessors. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:54-61 [Conf]
  36. David H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley Schuster
    Dynamically Tuning Processor Resources with Adaptive Processing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:12, pp:49-58 [Journal]
  37. Pradip Bose, Thomas M. Conte
    Performance Analysis and Its Impact on Design. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1998, v:31, n:5, pp:41-49 [Journal]
  38. David Brooks, Pradip Bose, Viji Srinivasan, Michael Gschwind, Philip G. Emma, Michael G. Rosenfield
    New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2003, v:47, n:5-6, pp:653-670 [Journal]
  39. Pradip Bose
    Pre-Silicon Modeling and Analysis: Impact On Real Design. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:4, pp:3- [Journal]
  40. Pradip Bose, David H. Albonesi, Diana Marculescu
    Guest Editors' Introduction: Power and Complexity Aware Design. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:5, pp:8-11 [Journal]
  41. Pradip Bose
    Designing reliable systems with unreliable components. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:5, pp:5-6 [Journal]
  42. Pradip Bose
    Looking Forward to Bright New Beginnings. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:1, pp:5-6 [Journal]
  43. Pradip Bose
    Issues and Trends in High-Performance Processor Cores. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:2, pp:5- [Journal]
  44. Pradip Bose
    Design and Integration: Chip- and System-Level Challenges. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:3, pp:5- [Journal]
  45. Pradip Bose
    Editor-in-Chief?s Message: Adapting Old Paradigms to Meet New Challenges. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:4, pp:5- [Journal]
  46. Pradip Bose
    Editor in Chief's Message: New Challenges and Burning Issues. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:1, pp:5- [Journal]
  47. Pradip Bose
    EIC's Message: Chip-level microarchitecture trends. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:2, pp:5-0 [Journal]
  48. Pradip Bose
    EIC's Message: General-purpose versus application-specific processors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:3, pp:5-0 [Journal]
  49. Pradip Bose
    Editor in Chief's Message: Saving power-Lessons from embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:4, pp:5-6 [Journal]
  50. Pradip Bose
    Communication versus Computation. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:5, pp:5- [Journal]
  51. Pradip Bose
    Computer architecture research: Shifting priorities and newer challenges. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:6, pp:5- [Journal]
  52. Pradip Bose
    The "power" of communication. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:1, pp:5- [Journal]
  53. Pradip Bose
    Variation-tolerant design. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:2, pp:5- [Journal]
  54. Pradip Bose
    Integrated microarchitectures. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:3, pp:5-6 [Journal]
  55. Pradip Bose
    Presilicon modeling: challenges in the late CMOS era. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:4, pp:5-6 [Journal]
  56. Pradip Bose
    High performance at affordable power. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:5, pp:5- [Journal]
  57. Pradip Bose
    Designing microprocessors with robust functionality and performance. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:6, pp:5- [Journal]
  58. Pradip Bose
    Measuring the impact of microarchitectural ideas. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:1, pp:5-6 [Journal]
  59. Pradip Bose
    Workload characterization: A key aspect of microarchitecture design. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:2, pp:5-6 [Journal]
  60. Pradip Bose
    Robust On-Chip Communication. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:3, pp:5- [Journal]
  61. David Brooks, Pradip Bose, Stanley Schuster, Hans M. Jacobson, Prabhakar Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor V. Zyuban, Manish Gupta, Peter W. Cook
    Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2000, v:20, n:6, pp:26-44 [Journal]
  62. Charles R. Moore, Kevin W. Rudd, Ruby B. Lee, Pradip Bose
    Guest Editors' Introduction: Micro's Top Picks from Microarchitecture Conferences. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:6, pp:8-10 [Journal]
  63. Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers
    Lifetime Reliability: Toward an Architectural Solution. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:3, pp:70-80 [Journal]
  64. Kunio Uchiyama, Pradip Bose
    Guest Editors' Introduction: Energy-Efficient Design. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:5, pp:6-9 [Journal]
  65. David Brooks, Pradip Bose, Margaret Martonosi
    Power-performance simulation: design and validation strategies. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS Performance Evaluation Review, 2004, v:31, n:4, pp:13-18 [Journal]
  66. Pradip Bose
    A Novel Technique for Efficient Parallel Implementation of a Classical Logic/Fault Simulation Problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:12, pp:1569-1577 [Journal]
  67. Victor V. Zyuban, David Brooks, Viji Srinivasan, Michael Gschwind, Pradip Bose, Philip N. Strenski, Philip G. Emma
    Integrated Analysis of Power and Performance for Pipelined Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:8, pp:1004-1016 [Journal]
  68. Jeonghee Shin, Victor V. Zyuban, Zhigang Hu, Jude A. Rivers, Pradip Bose
    A Framework for Architecture-Level Lifetime Reliability Modeling. [Citation Graph (0, 0)][DBLP]
    DSN, 2007, pp:534-543 [Conf]
  69. Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers
    Architecture-Level Soft Error Analysis: Examining the Limits of Common Assumptions. [Citation Graph (0, 0)][DBLP]
    DSN, 2007, pp:266-275 [Conf]
  70. Pradip Bose
    Looking briefly back, and then forward... [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:6, pp:8-9 [Journal]

  71. Systematically derived instruction sets for high-level language support. [Citation Graph (, )][DBLP]


  72. Exploring power management in multi-core systems. [Citation Graph (, )][DBLP]


  73. Performance and power evaluation of an in-line accelerator. [Citation Graph (, )][DBLP]


  74. Performance modeling for early analysis of multi-core systems. [Citation Graph (, )][DBLP]


  75. Power-efficient, reliable microprocessor architectures: modeling and design methods. [Citation Graph (, )][DBLP]


  76. A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime. [Citation Graph (, )][DBLP]


  77. Online Estimation of Architectural Vulnerability Factor for Soft Errors. [Citation Graph (, )][DBLP]


  78. Thermal-aware task scheduling at the system software level. [Citation Graph (, )][DBLP]


  79. Evaluating design tradeoffs in on-chip power management for CMPs. [Citation Graph (, )][DBLP]


  80. Dynamic power gating with quality guarantees. [Citation Graph (, )][DBLP]


  81. Metrics for Architecture-Level Lifetime Reliability Analysis. [Citation Graph (, )][DBLP]


  82. Tribeca: design for PVT variations with local recovery and fine-grained adaptation. [Citation Graph (, )][DBLP]


  83. Guest Editors' Introduction: Reliability Challenges in Nano-CMOS Design. [Citation Graph (, )][DBLP]


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