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David L. Dill: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rajeev Alur, David L. Dill
    A Theory of Timed Automata. [Citation Graph (3, 0)][DBLP]
    Theor. Comput. Sci., 1994, v:126, n:2, pp:183-235 [Journal]
  2. Rajeev Alur, David L. Dill
    Automata For Modeling Real-Time Systems. [Citation Graph (1, 0)][DBLP]
    ICALP, 1990, pp:322-335 [Conf]
  3. Jerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill, L. J. Hwang
    Symbolic Model Checking: 10^20 States and Beyond [Citation Graph (1, 0)][DBLP]
    Inf. Comput., 1992, v:98, n:2, pp:142-170 [Journal]
  4. Supratik Chakraborty, David L. Dill
    More Accurate Polynomial-Time Min-Max Timing Simulation. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1997, pp:112-0 [Conf]
  5. Supratik Chakraborty, David L. Dill, Kun-Yung Chang, Kenneth Y. Yun
    Timing Analysis of Extended Burst-Mode Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1997, pp:101-111 [Conf]
  6. Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill
    A New Reachability Algorithm for Symmetric Multi-processor Architecture. [Citation Graph (0, 0)][DBLP]
    ATVA, 2005, pp:26-38 [Conf]
  7. David L. Dill
    Timing Assumptions and Verification of Finite-State Concurrent Systems. [Citation Graph (0, 0)][DBLP]
    Automatic Verification Methods for Finite State Systems, 1989, pp:197-212 [Conf]
  8. Clark W. Barrett, David L. Dill, Aaron Stump
    A Framework for Cooperating Decision Procedures. [Citation Graph (0, 0)][DBLP]
    CADE, 2000, pp:79-98 [Conf]
  9. Aaron Stump, David L. Dill
    Faster Proof Checking in the Edinburgh Logical Framework. [Citation Graph (0, 0)][DBLP]
    CADE, 2002, pp:392-407 [Conf]
  10. Alan J. Hu, David L. Dill
    Efficient Verification with BDDs using Implicitly Conjoined Invariants. [Citation Graph (0, 0)][DBLP]
    CAV, 1993, pp:3-14 [Conf]
  11. C. Norris Ip, David L. Dill
    Verifying Systems with Replicated Components in Murphi. [Citation Graph (0, 0)][DBLP]
    CAV, 1996, pp:147-158 [Conf]
  12. Husam Abu-Haimed, Sergey Berezin, David L. Dill
    Strengthening Invariants by Symbolic Consistency Testing. [Citation Graph (0, 0)][DBLP]
    CAV, 2003, pp:407-419 [Conf]
  13. Clark W. Barrett, David L. Dill, Aaron Stump
    Checking Satisfiability of First-Order Formulas by Incremental Translation to SAT. [Citation Graph (0, 0)][DBLP]
    CAV, 2002, pp:236-249 [Conf]
  14. Satyaki Das, David L. Dill, Seungjoon Park
    Experience with Predicate Abstraction. [Citation Graph (0, 0)][DBLP]
    CAV, 1999, pp:160-171 [Conf]
  15. Jerry R. Burch, David L. Dill
    Automatic verification of Pipelined Microprocessor Control. [Citation Graph (0, 0)][DBLP]
    CAV, 1994, pp:68-80 [Conf]
  16. Jacob Chang, Sergey Berezin, David L. Dill
    Using Interface Refinement to Integrate Formal Verification into the Design Cycle. [Citation Graph (0, 0)][DBLP]
    CAV, 2004, pp:122-134 [Conf]
  17. Costas Courcoubetis, David L. Dill, Magda Chatzaki, Panagiotis Tzounakis
    Verification with Real-Time COSPAN. [Citation Graph (0, 0)][DBLP]
    CAV, 1992, pp:274-287 [Conf]
  18. David L. Dill, Alan J. Hu, Howard Wong-Toi
    Checking for Language Inclusion Using Simulation Preorders. [Citation Graph (0, 0)][DBLP]
    CAV, 1991, pp:255-265 [Conf]
  19. David L. Dill, Howard Wong-Toi
    Verification of Real-Time Systems by Successive Over and Under Approximation. [Citation Graph (0, 0)][DBLP]
    CAV, 1995, pp:409-422 [Conf]
  20. David L. Dill
    I Think I Voted: E-Voting vs. Democracy. [Citation Graph (0, 0)][DBLP]
    CAV, 2006, pp:2- [Conf]
  21. David L. Dill
    The Murphi Verification System. [Citation Graph (0, 0)][DBLP]
    CAV, 1996, pp:390-393 [Conf]
  22. David L. Dill
    Alternative Approaches to Hardware Verification (abstract). [Citation Graph (0, 0)][DBLP]
    CAV, 1999, pp:1- [Conf]
  23. Alan J. Hu, David L. Dill, Andreas J. Drexler, C. Han Yang
    Higher-Level Specification and Verification with BDDs. [Citation Graph (0, 0)][DBLP]
    CAV, 1992, pp:82-95 [Conf]
  24. Paul Loewenstein, David L. Dill
    Verification of a Multiprocessor Cache Protocol Using Simulation Relations and Higher-Order Logic. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:302-311 [Conf]
  25. Seungjoon Park, David L. Dill
    Protocol Verification by Aggregation of Distributed Transactions. [Citation Graph (0, 0)][DBLP]
    CAV, 1996, pp:300-310 [Conf]
  26. Jens U. Skakkebæk, Robert B. Jones, David L. Dill
    Formal Verification of Out-of-Order Execution Using Incremental Flushing. [Citation Graph (0, 0)][DBLP]
    CAV, 1998, pp:98-109 [Conf]
  27. Ulrich Stern, David L. Dill
    Parallelizing the Murphi Verifier. [Citation Graph (0, 0)][DBLP]
    CAV, 1997, pp:256-278 [Conf]
  28. Ulrich Stern, David L. Dill
    Using Magnatic Disk Instead of Main Memory in the Murphi Verifier. [Citation Graph (0, 0)][DBLP]
    CAV, 1998, pp:172-183 [Conf]
  29. Aaron Stump, Clark W. Barrett, David L. Dill
    CVC: A Cooperating Validity Checker. [Citation Graph (0, 0)][DBLP]
    CAV, 2002, pp:500-504 [Conf]
  30. Howard Wong-Toi, David L. Dill
    Synthesizing Processes and Schedulers from Temporal Specifications. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:272-281 [Conf]
  31. Cristian Cadar, Vijay Ganesh, Peter M. Pawlowski, David L. Dill, Dawson R. Engler
    EXE: automatically generating inputs of death. [Citation Graph (0, 0)][DBLP]
    ACM Conference on Computer and Communications Security, 2006, pp:322-335 [Conf]
  32. Husam Abu-Haimed, Sergey Berezin, David L. Dill
    Semi-formal Verification of Memory Systems by Symbolic Simulation. [Citation Graph (0, 0)][DBLP]
    CHARME, 2003, pp:158-163 [Conf]
  33. Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson
    Predictive Reachability Using a Sample-Based Approach. [Citation Graph (0, 0)][DBLP]
    CHARME, 2005, pp:388-392 [Conf]
  34. Kanna Shimizu, David L. Dill, Ching-Tsun Chou
    A Specification Methodology by a Collection of Compact Properties as Applied to the Intel® ItaniumTM Processor Bus Protocol. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:340-354 [Conf]
  35. Ulrich Stern, David L. Dill
    Automatic verification of the SCI cache coherence protocol. [Citation Graph (0, 0)][DBLP]
    CHARME, 1995, pp:21-34 [Conf]
  36. Ulrich Stern, David L. Dill
    Improved probabilistic verification by hash compaction. [Citation Graph (0, 0)][DBLP]
    CHARME, 1995, pp:206-224 [Conf]
  37. C. Norris Ip, David L. Dill
    Better Verification Through Symmetry. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:97-111 [Conf]
  38. David L. Dill, Patrick Lincoln
    Evolution as Design Engineer. [Citation Graph (0, 0)][DBLP]
    CMSB, 2003, pp:202-206 [Conf]
  39. Rajeev Alur, Costas Courcoubetis, Nicolas Halbwachs, David L. Dill, Howard Wong-Toi
    Minimization of Timed Transition Systems. [Citation Graph (0, 0)][DBLP]
    CONCUR, 1992, pp:340-354 [Conf]
  40. David L. Dill
    Hierarchical Models of Synchronous Circuits (Abstract). [Citation Graph (0, 0)][DBLP]
    CONCUR, 1994, pp:161- [Conf]
  41. Alan J. Hu, David L. Dill
    Reducing BDD Size by Exploiting Functional Dependencies. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:266-271 [Conf]
  42. Clark W. Barrett, David L. Dill, Jeremy R. Levitt
    A Decision Procedure for Bit-Vector Arithmetic. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:522-527 [Conf]
  43. Jerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill
    Sequential Circuit Verification Using Symbolic Model Checking. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:46-51 [Conf]
  44. C. Norris Ip, David L. Dill
    State Reduction Using Reversible Rules. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:564-567 [Conf]
  45. David L. Dill
    What's Between Simulation and Formal Verification? (Extended Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:328-329 [Conf]
  46. David L. Dill, Nate James, Shishpal Rawat, Gérard Berry, Limor Fix, Harry Foster, Rajeev K. Ranjan, Gunnar Stålmarck, Curt Widdoes
    Formal verification methods: getting around the brick wall. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:576-577 [Conf]
  47. Shankar G. Govindaraju, David L. Dill, Alan J. Hu, Mark Horowitz
    Approximate Reachability with BDDs Using Overlapping Projections. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:451-456 [Conf]
  48. Shankar G. Govindaraju, David L. Dill, Jules P. Bergmann
    Improved Approximate Reachability Using Auxiliary State Variables. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:312-316 [Conf]
  49. Alan J. Hu, Gary York, David L. Dill
    New Techniques for Efficient Verification with Implicitly Conjoined BDDs. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:276-282 [Conf]
  50. Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson
    Multi-threaded reachability. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:467-470 [Conf]
  51. Kanna Shimizu, David L. Dill
    Deriving a simulation input generator and a coverage metric from a formal specification. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:801-806 [Conf]
  52. Polly Siegel, Giovanni De Micheli, David L. Dill
    Automatic Technology Mapping for Generalized Fundamental-Mode Asynchronous Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:61-67 [Conf]
  53. Chris Wilson, David L. Dill
    Reliable verification using symbolic simulation with scalar values. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:124-129 [Conf]
  54. C. Han Yang, David L. Dill
    Validation with Guided Search of the State Space. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:599-604 [Conf]
  55. César Sánchez, Sriram Sankaranarayanan, Henny Sipma, Ting Zhang, David L. Dill, Zohar Manna
    Event Correlation: Language and Semantics. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2003, pp:323-339 [Conf]
  56. Jeffrey X. Su, David L. Dill, Clark W. Barrett
    Automatic Generation of Invariants in Processor Verification. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:377-388 [Conf]
  57. Robert B. Jones, Carl-Johan H. Seger, David L. Dill
    Self-Consistency Checking. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:159-171 [Conf]
  58. Robert B. Jones, Jens U. Skakkebæk, David L. Dill
    Reducing Manual Abstraction in Formal Verification of Out-of-Order Execution. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1998, pp:2-17 [Conf]
  59. Clark W. Barrett, David L. Dill, Jeremy R. Levitt
    Validity Checking for Combinations of Theories with Equality. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:187-201 [Conf]
  60. Satyaki Das, David L. Dill
    Counter-Example Based Predicate Discovery in Predicate Abstraction. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2002, pp:19-32 [Conf]
  61. Debashis Sahoo, Subramanian K. Iyer, Jawahar Jain, Christian Stangier, Amit Narayan, David L. Dill, E. Allen Emerson
    A Partitioning Methodology for BDD-Based Verification. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2004, pp:399-413 [Conf]
  62. Vijay Ganesh, Sergey Berezin, David L. Dill
    Deciding Presburger Arithmetic by Model Checking and Comparisons with Other Methods. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2002, pp:171-186 [Conf]
  63. Jeffrey X. Su, David L. Dill, Jens U. Skakkebæk
    Formally Verifying Data and Control with Weak Reachability Invariants. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1998, pp:387-402 [Conf]
  64. Kanna Shimizu, David L. Dill, Alan J. Hu
    Monitor-Based Formal Specification of PCI. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:335-353 [Conf]
  65. Chris Wilson, David L. Dill, Randal E. Bryant
    Symbolic Simulation with Approximate Values. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:470-485 [Conf]
  66. Husam Abu-Haimed, David L. Dill, Sergey Berezin
    A Refinement Method for Validity Checking of Quantified First-Order Formulas in Hardware Verification. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:145-152 [Conf]
  67. David L. Dill
    Model checking Java programs. [Citation Graph (0, 0)][DBLP]
    FMSP, 2000, pp:1- [Conf]
  68. David Y. W. Park, Jens U. Skakkebæk, Mats Per Erik Heimdahl, Barbara J. Czerny, David L. Dill
    Checking properties of safety critical specifications using efficient decision procedures. [Citation Graph (0, 0)][DBLP]
    FMSP, 1998, pp:34-43 [Conf]
  69. Seungjoon Park, Satyaki Das, David L. Dill
    Automatic Checking of Aggregation Abstractions Through State Enumeration. [Citation Graph (0, 0)][DBLP]
    FORTE, 1997, pp:207-222 [Conf]
  70. Ulrich Stern, David L. Dill
    A New Scheme for Memory-Efficient Probabilistic Verification. [Citation Graph (0, 0)][DBLP]
    FORTE, 1996, pp:333-348 [Conf]
  71. Clark W. Barrett, David L. Dill, Aaron Stump
    A Generalization of Shostak's Method for Combining Decision Procedures. [Citation Graph (0, 0)][DBLP]
    FroCos, 2002, pp:132-146 [Conf]
  72. David Y. W. Park, Jens U. Skakkebæk, David L. Dill
    Static Analysis to Identify Invariants in RSML Specifications. [Citation Graph (0, 0)][DBLP]
    FTRTFT, 1998, pp:133-142 [Conf]
  73. Rajeev Alur, Costas Courcoubetis, David L. Dill
    Model-Checking for Probabilistic Real-Time Systems (Extended Abstract). [Citation Graph (0, 0)][DBLP]
    ICALP, 1991, pp:115-126 [Conf]
  74. Jerry R. Burch, David L. Dill, Elizabeth Wolf, Giovanni De Micheli
    Modeling hierarchical combinational circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:612-617 [Conf]
  75. Supratik Chakraborty, David L. Dill
    Approximate algorithms for time separation of events. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:190-194 [Conf]
  76. Shankar G. Govindaraju, David L. Dill
    Counterexample-Guided Choice of Projections in Approximate Symbolic Model Checking. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:115-119 [Conf]
  77. Shankar G. Govindaraju, David L. Dill
    Verification by approximate forward and backward reachability. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:366-370 [Conf]
  78. Robert B. Jones, David L. Dill, Jerry R. Burch
    Efficient validity checking for processor verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:2-6 [Conf]
  79. Steven M. Nowick, David L. Dill
    Automatic Synthesis of Locally-Clocked Asynchronous State Machines. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:318-321 [Conf]
  80. Steven M. Nowick, David L. Dill
    Exact two-level minimization of hazard-free logic with multiple-input changes. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:626-630 [Conf]
  81. Ellen Sentovich, David L. Dill, Serdar Tasiran
    Formal verification meets simulation (tutorial abstract). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:221- [Conf]
  82. Kenneth Y. Yun, David L. Dill
    Automatic synthesis of 3D asynchronous state machines. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:576-580 [Conf]
  83. Kenneth Y. Yun, David L. Dill
    Unifying synchronous/asynchronous state machine synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:255-260 [Conf]
  84. Kenneth Y. Yun, Bill Lin, David L. Dill, Srinivas Devadas
    Performance-driven synthesis of asynchronous controllers. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:550-557 [Conf]
  85. C. Norris Ip, David L. Dill
    Efficient Verification of Symmetric Concurrent Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:230-234 [Conf]
  86. Mark E. Dean, David L. Dill, Mark Horowitz
    Self-Timed Logic Using Current-Sensing Completion Detection (CSCD). [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:187-191 [Conf]
  87. David L. Dill, Andreas J. Drexler, Alan J. Hu, C. Han Yang
    Protocol Verification as a Hardware Design Aid. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:522-525 [Conf]
  88. Kenneth L. McMillan, David L. Dill
    Algorithms for Interface Timing Verification. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:48-51 [Conf]
  89. Steven M. Nowick, David L. Dill
    Synthesis of Asynchronous State Machines Using A Local Clock. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:192-197 [Conf]
  90. Steven M. Nowick, Kenneth Y. Yun, David L. Dill
    Practical Asynchronous Controller Design. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:341-345 [Conf]
  91. Kenneth Y. Yun, David L. Dill
    A high-performance asynchronous SCSI controller. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:44-0 [Conf]
  92. Kenneth Y. Yun, David L. Dill, Steven M. Nowick
    Synthesis of 3D Asynchronous State Machines. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:346-350 [Conf]
  93. Richard C. Ho, C. Han Yang, Mark Horowitz, David L. Dill
    Architecture Validation for Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:404-413 [Conf]
  94. David Lie, Andy Chou, Dawson R. Engler, David L. Dill
    A simple method for extracting models for protocol code. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:192-203 [Conf]
  95. David L. Dill
    Model checking Java programs (abstract only). [Citation Graph (0, 0)][DBLP]
    ISSTA, 2000, pp:179- [Conf]
  96. David Y. W. Park, University Stern, Jens U. Skakkebæk, David L. Dill
    Java Model Checking. [Citation Graph (0, 0)][DBLP]
    ASE, 2000, pp:253-256 [Conf]
  97. Rajeev Alur, Costas Courcoubetis, David L. Dill
    Model-Checking for Real-Time Systems [Citation Graph (0, 0)][DBLP]
    LICS, 1990, pp:414-425 [Conf]
  98. Jerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill, L. J. Hwang
    Symbolic Model Checking: 10^20 States and Beyond [Citation Graph (0, 0)][DBLP]
    LICS, 1990, pp:428-439 [Conf]
  99. Satyaki Das, David L. Dill
    Successive Approximation of Abstract Transition Relations. [Citation Graph (0, 0)][DBLP]
    LICS, 2001, pp:51-60 [Conf]
  100. Aaron Stump, Clark W. Barrett, David L. Dill, Jeremy R. Levitt
    A Decision Procedure for an Extensional Theory of Arrays. [Citation Graph (0, 0)][DBLP]
    LICS, 2001, pp:29-37 [Conf]
  101. David L. Dill
    The battle of accountable voting systems. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2004, pp:105- [Conf]
  102. David L. Dill
    Complete Trace Structures. [Citation Graph (0, 0)][DBLP]
    Hardware Specification, Verification and Synthesis, 1989, pp:224-243 [Conf]
  103. Madanlal Musuvathi, David Y. W. Park, Andy Chou, Dawson R. Engler, David L. Dill
    CMC: A Pragmatic Approach to Model Checking Real Code. [Citation Graph (0, 0)][DBLP]
    OSDI, 2002, pp:- [Conf]
  104. Rajeev Alur, Costas Courcoubetis, David L. Dill
    Verifying Automata Specifications of Probabilistic Real-time Systems. [Citation Graph (0, 0)][DBLP]
    REX Workshop, 1991, pp:28-44 [Conf]
  105. Rajeev Alur, David L. Dill
    The Theory of Timed Automata. [Citation Graph (0, 0)][DBLP]
    REX Workshop, 1991, pp:45-73 [Conf]
  106. Seungjoon Park, David L. Dill
    An Executable Specification, Analyzer and Verifier for RMO (Relaxed Memory Order). [Citation Graph (0, 0)][DBLP]
    SPAA, 1995, pp:34-41 [Conf]
  107. Seungjoon Park, David L. Dill
    Verification of FLASH Cache Coherence Protocol by Aggregation of Distributed Transactions. [Citation Graph (0, 0)][DBLP]
    SPAA, 1996, pp:288-296 [Conf]
  108. Madanlal Musuvathi, David L. Dill
    An Incremental Heap Canonicalization Algorithm. [Citation Graph (0, 0)][DBLP]
    SPIN, 2005, pp:28-42 [Conf]
  109. Sergey Berezin, Vijay Ganesh, David L. Dill
    An Online Proof-Producing Decision Procedure for Mixed-Integer Linear Arithmetic. [Citation Graph (0, 0)][DBLP]
    TACAS, 2003, pp:521-536 [Conf]
  110. David L. Dill, Bruce Schneier, Barbara Simons
    Voting and technology: who gets to count your vote? [Citation Graph (0, 0)][DBLP]
    Commun. ACM, 2003, v:46, n:8, pp:29-31 [Journal]
  111. Poorvi L. Vora, Ben Adida, Ren Bucholz, David Chaum, David L. Dill, David Jefferson, Douglas W. Jones, William Lattin, Aviel D. Rubin, Michael I. Shamos, Moti Yung
    Evaluation of voting systems. [Citation Graph (0, 0)][DBLP]
    Commun. ACM, 2004, v:47, n:11, pp:144- [Journal]
  112. Jonathan P. Bowen, Ricky W. Butler, David L. Dill, Robert L. Glass, David Gries, Anthony Hall, Michael G. Hinchey, C. Michael Holloway, Daniel Jackson, Cliff B. Jones, Michael J. Lutz, David Lorge Parnas, John M. Rushby, Jeannette M. Wing, Pamela Zave
    An Invitation to Formal Methods. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1996, v:29, n:4, pp:16-30 [Journal]
  113. Kanna Shimizu, David L. Dill
    Using Formal Specifications for Functional Validation of Hardware Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:4, pp:96-106 [Journal]
  114. Shankar G. Govindaraju, David L. Dill
    Approximate Symbolic Model Checking using Overlapping Projections. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 1999, v:23, n:2, pp:- [Journal]
  115. Aaron Stump, Clark W. Barrett, David L. Dill
    Producing Proofs from an Arithmetic Decision Procedure in Elliptical LF. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2002, v:70, n:2, pp:- [Journal]
  116. David L. Dill, Steven M. Nowick, Robert F. Sproull
    Specification and Automatic Verification of Self-Timed Queues. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1992, v:1, n:1, pp:29-60 [Journal]
  117. C. Norris Ip, David L. Dill
    Better Verification Through Symmetry. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1996, v:9, n:1/2, pp:41-75 [Journal]
  118. C. Norris Ip, David L. Dill
    Verifying Systems with Replicated Components in Mur[b.phiv]. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1999, v:14, n:3, pp:273-310 [Journal]
  119. Robert B. Jones, Jens U. Skakkebæk, David L. Dill
    Formal Verification of Out-of-Order Execution with Incremental Flushing. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2002, v:20, n:2, pp:139-158 [Journal]
  120. Ulrich Stern, David L. Dill
    Parallelizing the Murj Verifier. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2001, v:18, n:2, pp:117-129 [Journal]
  121. Rajeev Alur, Costas Courcoubetis, David L. Dill
    Model-Checking in Dense Real-time [Citation Graph (0, 0)][DBLP]
    Inf. Comput., 1993, v:104, n:1, pp:2-34 [Journal]
  122. David L. Dill, Aviel D. Rubin
    Guest Editors' Introduction: E-Voting Security. [Citation Graph (0, 0)][DBLP]
    IEEE Security & Privacy, 2004, v:2, n:1, pp:22-23 [Journal]
  123. Seungjoon Park, David L. Dill
    Verification of Cache Coherence Protocols by Aggregation of Distributed Transactions. [Citation Graph (0, 0)][DBLP]
    Theory Comput. Syst., 1998, v:31, n:4, pp:355-376 [Journal]
  124. Michael C. Browne, Edmund M. Clarke, David L. Dill, Bud Mishra
    Automatic Verification of Sequential Circuits Using Temporal Logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:12, pp:1035-1044 [Journal]
  125. Seungjoon Park, David L. Dill
    An Executable Specification and Verifier for Relaxed Memory Order. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:2, pp:227-235 [Journal]
  126. Jerry R. Burch, Edmund M. Clarke, David E. Long, Kenneth L. McMillan, David L. Dill
    Symbolic model checking for sequential circuit verification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:4, pp:401-424 [Journal]
  127. Supratik Chakraborty, Kenneth Y. Yun, David L. Dill
    Timing analysis of asynchronous systems using time separation of events. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:8, pp:1061-1076 [Journal]
  128. Steven M. Nowick, David L. Dill
    Exact two-level minimization of hazard-free logic with multiple-input changes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:986-997 [Journal]
  129. Seungjoon Park, Satyaki Das, David L. Dill
    Automatic checking of aggregation abstractions through stateenumeration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1202-1210 [Journal]
  130. Kenneth Y. Yun, David L. Dill
    Automatic synthesis of extended burst-mode circuits. I.(Specification and hazard-free implementations). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:101-117 [Journal]
  131. Kenneth Y. Yun, David L. Dill
    Automatic synthesis of extended burst-mode circuits. II. (Automaticsynthesis). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:118-132 [Journal]
  132. Kenneth Y. Yun, Bill Lin, David L. Dill, Srinivas Devadas
    BDD-based synthesis of extended burst-mode controllers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:782-792 [Journal]
  133. Carolyn L. Talcott, David L. Dill
    Multiple Representations of Biological Processes. [Citation Graph (0, 0)][DBLP]
    , 2006, v:, n:, pp:221-245 [Journal]
  134. Vijay Ganesh, David L. Dill
    A Decision Procedure for Bit-Vectors and Arrays. [Citation Graph (0, 0)][DBLP]
    CAV, 2007, pp:519-531 [Conf]
  135. David L. Dill, Merrill Knapp, Pamela Gage, Carolyn L. Talcott, Keith Laderoute, Patrick Lincoln
    The Pathalyzer: A Tool for Analysis of Signal Transduction Pathways. [Citation Graph (0, 0)][DBLP]
    Systems Biology and Regulatory Genomics, 2005, pp:11-22 [Conf]

  136. Formal Verification and Biology. [Citation Graph (, )][DBLP]


  137. Towards program optimization through automated analysis of numerical precision. [Citation Graph (, )][DBLP]


  138. Automatic Formal Verification of Block Cipher Implementations. [Citation Graph (, )][DBLP]


  139. An implementation of three algorithms for timing verification based on automata emptiness. [Citation Graph (, )][DBLP]


  140. Model checking system software with CMC. [Citation Graph (, )][DBLP]


  141. A Retrospective on Murphi. [Citation Graph (, )][DBLP]


  142. Point/counterpoint: The U.S. should ban paperless electronic voting machines. [Citation Graph (, )][DBLP]


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