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Publications of Author

1. Ajay Khoche, Erik Brunvand
   Testing self-timed circuits using partial scan. [Citation Graph (0, 0)][DBLP]
   ASYNC, 1995, pp:160-169 [Conf]
   
2. Sandeep Pagey, Ajay Khoche, Erik Brunvand
   DFT for fast testing of self-timed control circuits. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 1995, pp:382-386 [Conf]
   
3. Ajay Khoche, Erik Brunvand
   ACT: A DFT Tool for Self-Timed Circuits. [Citation Graph (0, 0)][DBLP]
   ITC, 1997, pp:829-837 [Conf]
   
4. Ajay Khoche, Rohit Kapur, David Armstrong, Thomas W. Williams, Mick Tegethoff, Jochen Rivoir
   A new methodology for improved tester utilization. [Citation Graph (0, 0)][DBLP]
   ITC, 2001, pp:916-923 [Conf]
   
5. Erik H. Volkerink, Ajay Khoche, Linda A. Kamas, Jochen Rivoir, Hans G. Kerkhoff
   Tackling test trade-offs from design, manufacturing to market using economic modeling. [Citation Graph (0, 0)][DBLP]
   ITC, 2001, pp:1098-1107 [Conf]
   
6. Erik H. Volkerink, Ajay Khoche, Subhasish Mitra
   Packet-Based Input Test Data Compression Techniques. [Citation Graph (0, 0)][DBLP]
   ITC, 2002, pp:154-163 [Conf]
   
7. Ajay Khoche
   Session Abstract. [Citation Graph (0, 0)][DBLP]
   VTS, 2006, pp:152-153 [Conf]
   
8. Ajay Khoche, Erik Brunvand
   A partial scan methodology for testing self-timed circuits. [Citation Graph (0, 0)][DBLP]
   VTS, 1995, pp:283-289 [Conf]
   
9. Ajay Khoche, Erik Brunvand
   Critical hazard free test generation for asynchronous circuits. [Citation Graph (0, 0)][DBLP]
   VTS, 1997, pp:203-209 [Conf]
   
10. Ajay Khoche, Peter Muhmenthaler
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:288-289 [Conf]
    
11. Ajay Khoche, Mike Rodgers, Pete O'Neil
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:426- [Conf]
    
12. Ajay Khoche, Erik H. Volkerink, Jochen Rivoir, Subhasish Mitra
    Test Vector Compression Using EDA-ATE Synergies. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:97-102 [Conf]
    
13. Erik H. Volkerink, Ajay Khoche, Jochen Rivoir, Klaus D. Hilliges
    Test Economics for Multi-site Test with Modern Cost Reduction Techniques. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:411-416 [Conf]
    
14. Ajay Khoche
    Panel Summaries: Real-Time Volume Diagnostics--Requirements and Challenges. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:4, pp:315- [Journal]
    
15. Ajay Khoche, Sunil D. Sherlekar, G. Venkatesh, Raja Venkateswaran
    A Behavioral Fault Simulator for Ideal. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1992, v:9, n:4, pp:14-21 [Journal]