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Subhasish Mitra: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen, Marly Roncken
    DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:73-0 [Conf]
  2. Subhasish Mitra, Tanay Karnik, Norbert Seifert, Ming Zhang
    Logic soft errors in sub-65nm technologies design and CAD challenges. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:2-4 [Conf]
  3. Erik H. Volkerink, Subhasish Mitra
    Response compaction with any number of unknowns using a new LFSR architecture. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:117-122 [Conf]
  4. Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey
    Testing Digital Circuits with Constraints. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:195-206 [Conf]
  5. Wei-Je Huang, Subhasish Mitra, Edward J. McCluskey
    Fast Run-Time Fault Location in Dependable FPGA-Based Applications. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:206-214 [Conf]
  6. Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
    Techniques for Estimation of Design Diversity for Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DSN, 2001, pp:25-36 [Conf]
  7. Subhasish Mitra, Edward J. McCluskey
    Dependable Reconfigurable Computing Design Diversity and Self Repair. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2002, pp:5- [Conf]
  8. Mehdi Baradaran Tahoori, Subhasish Mitra
    Defect and Fault Tolerance of Reconfigurable Molecular Computing. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:176-185 [Conf]
  9. Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey
    An output encoding problem and a solution technique. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:304-307 [Conf]
  10. Subhasish Mitra, Kee Sup Kim
    XMAX: X-Tolerant Architecture for MAXimal Test Compression. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:326-330 [Conf]
  11. T. M. Mak, Subhasish Mitra, Ming Zhang
    DFT Assisted Built-In Soft Error Resilience. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:69- [Conf]
  12. T. M. Mak, Subhasish Mitra
    Should Logic SER be Solved at the Circuit Level? [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:199- [Conf]
  13. Subhasish Mitra, Edward J. McCluskey
    Diversity Techniques for Concurrent Error Detection. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:249-250 [Conf]
  14. Kenneth A. Brand, Erik H. Volkerink, Edward J. McCluskey, Subhasish Mitra
    Speed Clustering of Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1128-1137 [Conf]
  15. Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
    A design diversity metric and reliability analysis for redundant systems. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:662-671 [Conf]
  16. Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey
    Scan Synthesis for One-Hot Signals. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:714-722 [Conf]
  17. Subhasish Mitra, Kee Sup Kim
    X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:311-320 [Conf]
  18. Subhasish Mitra, Steven S. Lumetta, Michael Mitzenmacher
    X-Tolerant Signature Analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:432-441 [Conf]
  19. Subhasish Mitra, Edward J. McCluskey
    Combinational logic synthesis for diversity in duplex systems. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:179-188 [Conf]
  20. Subhasish Mitra, Edward J. McCluskey
    Which concurrent error detection scheme to choose ? [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:985-994 [Conf]
  21. Mehdi Baradaran Tahoori, Subhasish Mitra
    Interconnect Delay Testing of Designs on Programmable Logic Devices. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:635-644 [Conf]
  22. Mehdi Baradaran Tahoori, Subhasish Mitra, Shahin Toutounchi, Edward J. McCluskey
    Fault Grading FPGA Interconnect Test Configurations. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:608-617 [Conf]
  23. Erik H. Volkerink, Ajay Khoche, Subhasish Mitra
    Packet-Based Input Test Data Compression Techniques. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:154-163 [Conf]
  24. David M. Wu, Mike Lin, Subhasish Mitra, Kee Sup Kim, Anil Sabbavarapu, Talal Jaber, Pete Johnson, Dale March, Greg Parrish
    H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1229-1238 [Conf]
  25. Bob Mungamuru, Hector Garcia-Molina, Subhasish Mitra
    How To Safeguard Your Sensitive Data. [Citation Graph (0, 0)][DBLP]
    SRDS, 2006, pp:199-211 [Conf]
  26. R. D. (Shawn) Blanton, Subhasish Mitra
    Testing Nanometer Digital Integration Circuits: Myths, Reality and the Road Ahead. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:8-9 [Conf]
  27. Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey
    Bist Reseeding with very few Seeds. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:69-76 [Conf]
  28. Ruifeng Guo, Subhasish Mitra, Enamul Amyeen, Jinkyu Lee, Srihari Sivaraj, Srikanth Venkataraman
    Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate Exhaustive. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:66-71 [Conf]
  29. Ajay Khoche, Erik H. Volkerink, Jochen Rivoir, Subhasish Mitra
    Test Vector Compression Using EDA-ATE Synergies. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:97-102 [Conf]
  30. Edward J. McCluskey, Subhasish Mitra, Bob Madge, Peter C. Maxwell, Phil Nigh, Mike Rodgers
    Debating the Future of Burn-In. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:311-314 [Conf]
  31. Edward J. McCluskey, Ahmad A. Al-Yamani, Chien-Mo James Li, Chao-Wen Tseng, Erik H. Volkerink, Francois-Fabien Ferhani, Edward Li, Subhasish Mitra
    ELF-Murphy Data on Defects and Test Sets. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:16-22 [Conf]
  32. Subhasish Mitra, Edward J. McCluskey
    Word Voter: A New Voter Design for Triple Modular Redundant Systems. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:465-470 [Conf]
  33. Subhasish Mitra, Edward J. McCluskey
    Design Diversity for Concurrent Error Detection in Sequential Logic Circuts. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:178-183 [Conf]
  34. Subhasish Mitra, Edward J. McCluskey
    Design of Redundant Systems Protected Against Common-Mode Failures. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:190-197 [Conf]
  35. Subhasish Mitra, Edward J. McCluskey, Samy Makar
    Design for Testability and Testing of IEEE 1149.1 Tap Controller. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:247-252 [Conf]
  36. Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
    Fault Escapes in Duplex Systems. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:453-458 [Conf]
  37. Subhasish Mitra, Erik H. Volkerink, Edward J. McCluskey, Stefan Eichenberger
    Delay Defect Screening using Process Monitor Structures. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:43-52 [Conf]
  38. Mehdi Baradaran Tahoori, Subhasish Mitra
    Automatic Configuration Generation for FPGA Interconnect Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:134-144 [Conf]
  39. Chao-Wen Tseng, Subhasish Mitra, Edward J. McCluskey, Scott Davidson
    An Evaluation of Pseudo Random Testing for Detecting Real Defects. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:404-410 [Conf]
  40. Erik H. Volkerink, Subhasish Mitra
    Efficient Seed Utilization for Reseeding based Compression. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:232-240 [Conf]
  41. Mridul Agarwal, Bipul C. Paul, Ming Zhang, Subhasish Mitra
    Circuit Failure Prediction and Its Application to Transistor Aging. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:277-286 [Conf]
  42. Subhasish Mitra, Norbert Seifert, Ming Zhang, Quan Shi, Kee Sup Kim
    Subhasish Mitra, Norbert Seifert, Ming Zhang, Quan Shi, Kee Sup Kim. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2005, v:38, n:2, pp:43-52 [Journal]
  43. Vladimir Hahanov, Raimund Ubar, Subhasish Mitra
    Conference Reports. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:6, pp:594-595 [Journal]
  44. Kee Sup Kim, Subhasish Mitra, Paul G. Ryan
    Delay Defect Characteristics and Testing Strategies. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:5, pp:8-16 [Journal]
  45. Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey
    Efficient Multiplexer Synthesis Techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:4, pp:90-97 [Journal]
  46. Subhasish Mitra, Wei-Je Huang, Nirmal R. Saxena, Shu-Yi Yu, Edward J. McCluskey
    Reconfigurable Architecture for Autonomous Self-Repair. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:228-240 [Journal]
  47. Subhasish Mitra, Steven S. Lumetta, Michael Mitzenmacher, Nishant Patil
    X-Tolerant Test Response Compaction. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:6, pp:566-574 [Journal]
  48. Nirmal R. Saxena, Santiago Fernández-Gomez, Wei-Je Huang, Subhasish Mitra, Shu-Yi Yu, Edward J. McCluskey
    Dependable Computing and Online Testing in Adaptive and Configurable Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:1, pp:29-41 [Journal]
  49. Ravishankar K. Iyer, Nithin Nakka, Zbigniew Kalbarczyk, Subhasish Mitra
    Recent Advances and New Avenues in Hardware-Level Reliability Support. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:6, pp:18-29 [Journal]
  50. Subhasish Mitra, Kee Sup Kim
    XPAND: An Efficient Test Stimulus Compression Technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:2, pp:163-173 [Journal]
  51. Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
    A Design Diversity Metric and Analysis of Redundant Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:5, pp:498-510 [Journal]
  52. Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
    Efficient Design Diversity Estimation for Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:11, pp:1483-1492 [Journal]
  53. Nahmsuk Oh, Subhasish Mitra, Edward J. McCluskey
    ED4I: Error Detection by Diverse Data and Duplicated Instructions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:2, pp:180-199 [Journal]
  54. Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey
    Optimized reseeding by seed ordering and encoding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:264-270 [Journal]
  55. Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey
    An output encoding problem and a solution technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:761-768 [Journal]
  56. Subhasish Mitra, Kee Sup Kim
    X-compact: an efficient response compaction technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:421-432 [Journal]
  57. Mehdi Baradaran Tahoori, Subhasish Mitra
    Techniques and algorithms for fault grading of FPGA interconnect test configurations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:261-272 [Journal]
  58. Mehdi Baradaran Tahoori, Subhasish Mitra
    Application-independent testing of FPGA interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1774-1783 [Journal]
  59. Nishant Patil, Jie Deng, H.-S. Philip Wong, Subhasish Mitra
    Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:958-961 [Conf]
  60. Sanjit A. Seshia, Wenchao Li, Subhasish Mitra
    Verification-guided soft error resilience. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1442-1447 [Conf]
  61. Subhasish Mitra, Pia Sanda, Norbert Seifert
    Soft Errors: Technology Trends, System Effects, and Protection Techniques. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:4- [Conf]
  62. Subhasish Mitra
    Circuit Failure Prediction Enables Robust System Design Resilient to Aging and Wearout. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:123- [Conf]
  63. Subhasish Mitra, Ming Zhang, Norbert Seifert, T. M. Mak, Kee Sup Kim
    Soft Error Resilient System Design through Error Correction. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:332-337 [Conf]
  64. Ming Zhang, Subhasish Mitra, T. M. Mak, Norbert Seifert, N. J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, S. J. Patel
    Sequential Element Design With Built-In Soft Error Resilience. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1368-1378 [Journal]

  65. IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors. [Citation Graph (, )][DBLP]


  66. Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions. [Citation Graph (, )][DBLP]


  67. Carbon nanotube circuits in the presence of carbon nanotube density variations. [Citation Graph (, )][DBLP]


  68. Post-silicon validation opportunities, challenges and recent advances. [Citation Graph (, )][DBLP]


  69. Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement. [Citation Graph (, )][DBLP]


  70. BLoG: post-silicon bug localization in processors using bug localization graphs. [Citation Graph (, )][DBLP]


  71. Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits. [Citation Graph (, )][DBLP]


  72. CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns. [Citation Graph (, )][DBLP]


  73. Globally Optimized Robust Systems to Overcome Scaled CMOS Reliability Challenges. [Citation Graph (, )][DBLP]


  74. Soft Errors: System Effects, Protection Techniques and Case Studies. [Citation Graph (, )][DBLP]


  75. Dependable Embedded Systems Special Day Panel: Issues and Challenges in Dependable Embedded Systems. [Citation Graph (, )][DBLP]


  76. Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors. [Citation Graph (, )][DBLP]


  77. Statistical static timing analysis using Markov chain Monte Carlo. [Citation Graph (, )][DBLP]


  78. ERSA: Error Resilient System Architecture for probabilistic applications. [Citation Graph (, )][DBLP]


  79. Optimized self-tuning for circuit aging. [Citation Graph (, )][DBLP]


  80. Carbon nanotube circuits: Living with imperfections and variations. [Citation Graph (, )][DBLP]


  81. Cross-layer resilience challenges: Metrics and optimization. [Citation Graph (, )][DBLP]


  82. Efficient FPGAs using nanoelectromechanical relays. [Citation Graph (, )][DBLP]


  83. Reliable system design: models, metrics and design techniques. [Citation Graph (, )][DBLP]


  84. A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. [Citation Graph (, )][DBLP]


  85. Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage. [Citation Graph (, )][DBLP]


  86. Operating system scheduling for efficient online self-test in robust systems. [Citation Graph (, )][DBLP]


  87. Soft Error Protection Techniques. [Citation Graph (, )][DBLP]


  88. Tutorial 4: Robust System Design in Scaled CMOS. [Citation Graph (, )][DBLP]


  89. Robust System Design. [Citation Graph (, )][DBLP]


  90. Gate-Oxide Early Life Failure Prediction. [Citation Graph (, )][DBLP]


  91. Post-silicon bug localization for processors using IFRA. [Citation Graph (, )][DBLP]


  92. Historical Perspective on Scan Compression. [Citation Graph (, )][DBLP]


  93. The Search for Alternative Computational Paradigms. [Citation Graph (, )][DBLP]


  94. Overcoming Early-Life Failure and Aging for Robust Systems. [Citation Graph (, )][DBLP]


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