The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Hubert Kaeslin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Thomas Villiger, Hubert Kaeslin, Frank K. Gürkaynak, Stephan Oetiker, Wolfgang Fichtner
    Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:141-150 [Conf]
  2. Thomas Villiger, Stephan Oetiker, Frank K. Gürkaynak, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
    A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:181-189 [Conf]
  3. Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
    GALS at ETH Zurich: Success or Failure. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2006, pp:150-159 [Conf]
  4. A. K. Lutz, J. Treichler, Frank K. Gürkaynak, Hubert Kaeslin, G. Basler, Antonia Erni, S. Reichmuth, P. Rommens, Stephan Oetiker, Wolfgang Fichtner
    2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:144-158 [Conf]
  5. Felix Bürgin, Flavio Carbognani, Martin Hediger, Hektor Meier, Robert Meyer-Piening, Rafael Santschi, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
    Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:558-561 [Conf]
  6. Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
    Two-phase resonant clocking for ultra-low-power hearing aid applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:73-78 [Conf]
  7. Frank K. Gürkaynak, Andreas Burg, Norbert Felber, Wolfgang Fichtner, D. Gasser, F. Hug, Hubert Kaeslin
    A 2 Gb/s balanced AES crypto-chip implementation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:39-44 [Conf]
  8. H. Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, Xuejia Lai
    VLSI Implementation of a New Block Cipher. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:510-513 [Conf]
  9. Andreas Burg, Frank K. Gürkaynak, Hubert Kaeslin, Wolfgang Fichtner
    Variable delay ripple carry adder with carry chain interrupt detection. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:113-116 [Conf]
  10. H. Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, R. Zimmermann, Wolfgang Fichtner
    VINCI: Secure Test of a VLSI High-Speed Encryption System. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:782-790 [Conf]
  11. Manfred Stadler, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, Markus Thalmann
    Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:414-420 [Conf]
  12. Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
    Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:446-455 [Conf]
  13. Robert Rogenmoser, Hubert Kaeslin, Tobias Blickle
    Stochastic Methods for Transistor Size Optimization of CMOS VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    PPSN, 1996, pp:849-858 [Conf]
  14. Hubert Kaeslin
    Application of Graph Theory to Topology Generation for Logic Gates. [Citation Graph (0, 0)][DBLP]
    WG, 1988, pp:304-316 [Conf]
  15. Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
    Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2006, v:146, n:2, pp:133-149 [Journal]
  16. Manfred Stadler, Markus Thalmann, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
    Design and Verification of a Stack Processor Virtual Component. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2001, v:21, n:2, pp:69-80 [Journal]
  17. Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
    42% power savings through glitch-reducing clocking strategy in a hearing aid application. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  18. Tim Weyrich, Cyril Flaig, Simon Heinzle, Simon Mall, Timo Aila, Kaspar Rohrer, Daniel B. Fasnacht, Norbert Felber, Stephan Oetiker, Hubert Kaeslin, Mario Botsch, Markus H. Gross
    A hardware architecture for surface splatting. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Graph., 2007, v:26, n:3, pp:90- [Journal]

Search in 0.017secs, Finished in 0.019secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002