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Publications of Author

1. Tony Werner, Venkatesh Akella
   An Asynchronous Superscalar Architecture for Exploiting Instruction-Level Parallelism. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2001, pp:140-151 [Conf]
   
2. Ganesh Gopalakrishnan, Narayana Mani, Venkatesh Akella
   Parallel Composition of Lockstep Synchronous Processes for Hardware Validation: Divide-and-Conquer Composition. [Citation Graph (0, 0)][DBLP]
   Automatic Verification Methods for Finite State Systems, 1989, pp:374-382 [Conf]
   
3. John Oliver, Ravishankar Rao, Michael Brown, Jennifer Mankin, Diana Franklin, Frederic T. Chong, Venkatesh Akella
   Tile size selection for low-power tile-based architectures. [Citation Graph (0, 0)][DBLP]
   Conf. Computing Frontiers, 2006, pp:83-94 [Conf]
   
4. John Oliver, Venkatesh Akella
   Improving DSP Performance with a Small Amount of Field Programmable Logic. [Citation Graph (0, 0)][DBLP]
   FPL, 2003, pp:520-532 [Conf]
   
5. Venkatesh Akella, Nitin H. Vaidya, G. Robert Redinbo
   Limitations of VLSI Implementation of Delay-Insensitive Codes. [Citation Graph (0, 0)][DBLP]
   FTCS, 1996, pp:208-217 [Conf]
   
6. Ravishankar Rao, Justin Wenck, Diana Franklin, Rajeevan Amirtharajah, Venkatesh Akella
   Segmented Bitline Cache: Exploiting Non-uniform Memory Access Patterns. [Citation Graph (0, 0)][DBLP]
   HiPC, 2006, pp:123-134 [Conf]
   
7. Venkatesh Akella, Ganesh Gopalakrishnan
   SHILPA: a high-level synthesis system for self-timed circuits. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1992, pp:587-591 [Conf]
   
8. Prabhakar Kudva, Ganesh Gopalakrishnan, Erik Brunvand, Venkatesh Akella
   Performance Analysis and Optimization of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
   ICCD, 1994, pp:221-224 [Conf]
   
9. Bret Stott, Dave Johnson, Venkatesh Akella
   Asynchronous 2-D discrete cosine transform core processor. [Citation Graph (0, 0)][DBLP]
   ICCD, 1995, pp:380-385 [Conf]
   
10. Mihaela van der Schaar, Deepak S. Turaga, Venkatesh Akella
    Rate-distortion-complexity adaptive video compression and streaming. [Citation Graph (0, 0)][DBLP]
    ICIP, 2004, pp:2051-2054 [Conf]
    
11. John Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Franklin, Venkatesh Akella, Frederic T. Chong
    Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:150-161 [Conf]
    
12. John Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Dean Copsey, Diana Keen, Venkatesh Akella, Frederic T. Chong
    Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture. [Citation Graph (0, 0)][DBLP]
    PACS, 2003, pp:73-85 [Conf]
    
13. John Oliver, Venkatesh Akella, Frederic T. Chong
    Efficient orchestration of sub-word parallelism in media processors. [Citation Graph (0, 0)][DBLP]
    SPAA, 2004, pp:225-234 [Conf]
    
14. Ganesh Gopalakrishnan, Venkatesh Akella
    A transformational approach to asynchronous high-level synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI, 1993, pp:201-210 [Conf]
    
15. Nithya Raghavan, Venkatesh Akella, Smita Bakshi
    Automatic Insertion of Gated Clocks at Register Transfer Level. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:48-54 [Conf]
    
16. Tony Werner, Venkatesh Akella
    Asynchronous Processor Survey. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:11, pp:67-76 [Journal]
    
17. Venkatesh Akella, Ganesh Gopalakrishnan
    CFSIM: A Concurrent Compiled Code Functional Simulator for hopCP. [Citation Graph (0, 0)][DBLP]
    Int. Journal in Computer Simulation, 1994, v:4, n:4, pp:0-0 [Journal]
    
18. Venkatesh Akella, Nitin H. Vaidya, G. Robert Redinbo
    Asynchronous Comparison-Based Decoders for Delay-Insensitive Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:7, pp:802-811 [Journal]
    
19. Venkatesh Akella, Ganesh Gopalakrishnan
    Specification and Validation of Control-Intensive IC's in hopCP. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1994, v:20, n:6, pp:405-423 [Journal]
    
20. Dave Johnson, Venkatesh Akella, Bret Stott
    Micropipelined asynchronous discrete cosine transform (DCT/IDCT) processor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:731-740 [Journal]
    
21. 
    Credit-based dynamic reliability management using online wearout detection. [Citation Graph (, )][DBLP]
    
    
22. 
    Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing. [Citation Graph (, )][DBLP]
    
    
23. 
    Markov decision process (MDP) framework for optimizing software on mobile phones. [Citation Graph (, )][DBLP]
    
    
24. 
    OCDIMM: Scaling the DRAM Memory Wall Using WDM Based Optical Interconnects. [Citation Graph (, )][DBLP]
    
    
25. 
    Design and evaluation of an optical CPU-DRAM interconnect. [Citation Graph (, )][DBLP]
    
    
26. 
    Proactive Energy Optimization Algorithms for Wavelet-Based Video Codecs on Power-Aware Processors. [Citation Graph (, )][DBLP]
    
    
27. 
    Performance Evaluation of a Multicore System with Optically Connected Memory Modules. [Citation Graph (, )][DBLP]
    
    
28. 
    Life Cycle Aware Computing: Reusing Silicon Technology. [Citation Graph (, )][DBLP]