The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Peter Y. K. Cheung: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Pedro A. Molina, Peter Y. K. Cheung
    A Quasi Delay-Insensitive Bus Proposal for Asynchronous Systems. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1997, pp:126-139 [Conf]
  2. Ray C. C. Cheung, Dong-U Lee, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung
    Automating custom-precision function evaluation for embedded processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:22-31 [Conf]
  3. Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung
    Flexible instruction processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:193-200 [Conf]
  4. Sutjipto Arifin, Peter Y. K. Cheung
    A novel FPGA-based implementation of time adaptive clustering for logical story unit segmentation. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:227-232 [Conf]
  5. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Heuristic datapath allocation for multiple wordlength systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:791-797 [Conf]
  6. Ray C. C. Cheung, Wayne Luk, Peter Y. K. Cheung
    Reconfigurable Elliptic Curve Cryptosystems on a Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:24-29 [Conf]
  7. Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk
    Hardware Acceleration of Hidden Markov Model Decoding for Person Detection. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:8-13 [Conf]
  8. Sambuddhi Hettiaratchi, Peter Y. K. Cheung
    Mesh Partitioning Approach to Energy Efficient Data Layout. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11076-11081 [Conf]
  9. Sambuddhi Hettiaratchi, Peter Y. K. Cheung
    A Novel Implementation of Tile-Based Address Mapping. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:306-311 [Conf]
  10. Sambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas J. W. Clarke
    Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:902-908 [Conf]
  11. Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung, Philip Heng Wai Leong, Stephen J. Motley
    Hardware efficient architectures for Eigenvalue computation. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:953-958 [Conf]
  12. Wim J. C. Melis, Kieron Turkington, Alexander Whitton, Wayne Luk, Peter Y. K. Cheung, Paul Metzgen
    Cell Based Motion Estimators for Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    ERSA, 2005, pp:218-224 [Conf]
  13. Tero Rissa, Wayne Luk, Peter Y. K. Cheung
    Distinguished Paper: Automated Combination of Simulation and Hardware Prototyping. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:184-193 [Conf]
  14. Salman Ahmed, Peter Y. K. Cheung, Phil Collins
    A Model-based Approach to Analog Fault Diagnosis using Techniques from Optimisation. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:665- [Conf]
  15. Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi
    Customising Floating-Point Designs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:315-317 [Conf]
  16. Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung
    Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:79-88 [Conf]
  17. Jörn Gause, Peter Y. K. Cheung, Wayne Luk
    Reconfigurable Shape-Adaptive Template Matching Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:98-0 [Conf]
  18. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Multiple Precision for Resource Minimization. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:307-308 [Conf]
  19. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Optimum Wordlength Allocation. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:219-228 [Conf]
  20. Christos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung
    A Novel 2D Filter Design Methodology for Heterogeneous Devices. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:13-22 [Conf]
  21. Simon D. Haynes, Peter Y. K. Cheung
    A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:226-0 [Conf]
  22. Simon D. Haynes, Peter Y. K. Cheung, Wayne Luk, John Stone
    SONIC - A Plug-In Architecture for Video Processing. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:280-281 [Conf]
  23. Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung
    A Hardware Gaussian Noise Generator for Channel Code Evaluation. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:69-0 [Conf]
  24. Wayne Luk, T. K. Lee, J. Rice, Nabeel Shirazi, Peter Y. K. Cheung
    Reconfigurable Computing for Augmented Reality. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:136-145 [Conf]
  25. Wayne Luk, Nabeel Shirazi, Peter Y. K. Cheung
    Compilation tools for run-time reconfigurable designs. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:56-65 [Conf]
  26. Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung
    Migrating Functionality from ROMS to Embedded Multipliers. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:287-288 [Conf]
  27. Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk
    Image Registration of Real-Time Video Data Using the SONIC Reconfigurable Computer Platform. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:3-12 [Conf]
  28. Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk
    Tabu Search with Intensification Strategy for Functional Partitioning in Hardware-Software Codesign. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:297-298 [Conf]
  29. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
    A Structured System Methodology for FPGA Based System-on-A-Chip Design. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:271-272 [Conf]
  30. Nabeel Shirazi, Wayne Luk, Peter Y. K. Cheung
    Automating Production of Run-Time Reconfigurable Designs. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:147-0 [Conf]
  31. Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
    A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:275-276 [Conf]
  32. Hasan Demirel, Thomas J. Clarke, Peter Y. K. Cheung
    Adaptive Automatic Facial Feature Segmentation. [Citation Graph (0, 0)][DBLP]
    FG, 1996, pp:277-282 [Conf]
  33. Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
    Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:138-148 [Conf]
  34. Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
    Yield enhancements of design-specific FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:93-100 [Conf]
  35. Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
    Exploration of heterogeneous reconfigurable architectures (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:268- [Conf]
  36. N. Pete Sedcole, Peter Y. K. Cheung
    Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis. [Citation Graph (0, 0)][DBLP]
    FPGA, 2007, pp:178-187 [Conf]
  37. Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides
    Heterogeneity Exploration for Multiple 2D Filter Designs. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:263-268 [Conf]
  38. Christos-Savvas Bouganis, Peter Y. K. Cheung, Jeffrey Ng, Anil A. Bharath
    A Steerable Complex Wavelet Construction and Its Implementation on FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:394-403 [Conf]
  39. Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides
    Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:200-208 [Conf]
  40. Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
    Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:409-414 [Conf]
  41. Nicola Campregher, Peter Y. K. Cheung, Milan Vasilko
    BIST Based Interconnect Fault Location for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:322-332 [Conf]
  42. Anjit Sekhar Chaudhuri, Peter Y. K. Cheung, Wayne Luk
    A reconfigurable data-localised array for morphological algorithms. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:344-353 [Conf]
  43. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Multiple-Wordlength Resource Binding. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:646-655 [Conf]
  44. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Synthia: Synthesis of Interacting Automata Targeting LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:323-332 [Conf]
  45. Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides
    Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:124-129 [Conf]
  46. Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk
    Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:142-147 [Conf]
  47. Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi, James Hwang
    Automating Customisation of Floating-Point Designs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:523-533 [Conf]
  48. Simon D. Haynes, Peter Y. K. Cheung, Wayne Luk, John Stone
    SONIC - A Plug-In Architecture for Video Processing. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:21-30 [Conf]
  49. Jörn Gause, Peter Y. K. Cheung, Wayne Luk
    Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:96-105 [Conf]
  50. Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung
    Non-uniform Segmentation for Hardware Function Evaluation. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:796-807 [Conf]
  51. Wayne Luk, Nabeel Shirazi, Shaori Guo, Peter Y. K. Cheung
    Pipeline morphing and virtual pipelines. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:111-120 [Conf]
  52. Patrick I. Mackinlay, Peter Y. K. Cheung, Wayne Luk, Richard Sandiford
    Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:91-100 [Conf]
  53. Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk
    Image Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable Computer. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1148-1151 [Conf]
  54. Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung
    Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:77-82 [Conf]
  55. Andrew Royal, Peter Y. K. Cheung
    Globally Asynchronous Locally Synchronous FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:355-364 [Conf]
  56. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
    A Reconfigurable Platform for Real-Time Embedded Video Image Processing. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:606-615 [Conf]
  57. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
    A Structured Methodology for System-on-an-FPGA Design. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1047-1051 [Conf]
  58. Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung
    Run-Time Adaptive Flexible Instruction Processors. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:545-555 [Conf]
  59. Tero Rissa, Peter Y. K. Cheung, Wayne Luk
    SoftSONIC: A Customisable Modular Platform for Video Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:54-63 [Conf]
  60. Nabeel Shirazi, Wayne Luk, Dan Benyamin, Peter Y. K. Cheung
    Quantitative Analysis of Run-Time Reconfigurable Database Search. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:253-263 [Conf]
  61. Nabeel Shirazi, Wayne Luk, Peter Y. K. Cheung
    Run-Time Management of Dynamically Recongigurable Designs. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:59-68 [Conf]
  62. Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung
    Multiple Restricted Multiplication. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:374-383 [Conf]
  63. Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung
    Power and Area Optimization for Multiple Restricted Multiplication. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:112-117 [Conf]
  64. Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
    An Analytical Approach to Generation and Exploration of Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:341-346 [Conf]
  65. Chakkapas Visavakul, Peter Y. K. Cheung, Wayne Luk
    A Digit-Serial Structure for Reconfigurable Multipliers. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:565-573 [Conf]
  66. Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk
    A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:396-405 [Conf]
  67. Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk
    Cluster-Driven Hardware/Software Partitioning and Scheduling Approach for a Reconfigurable Computer System. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1071-1074 [Conf]
  68. Ben Cope, Peter Y. K. Cheung, Wayne Luk, Sarah Witt
    Have GPUs Made FPGAs Redundant in the Field of Video Processing? [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:111-118 [Conf]
  69. Laurence A. Hey, Peter Y. K. Cheung, Michael Gellman
    FPGA Based Router for Cognitive Packet Networks. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:331-332 [Conf]
  70. Sambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas J. W. Clarke
    Energy efficient address assignment through minimized memory row switching. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:577-581 [Conf]
  71. David S. Bormann, Peter Y. K. Cheung
    Asnchronous Wrapper for Heterogeneous Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:307-314 [Conf]
  72. Osama T. Albaharna, Peter Y. K. Cheung, Thomas J. Clarke
    Area & Time Limitations of FPGA-based Virtual Hardware. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:184-189 [Conf]
  73. Vicente Fuentes-Sánchez, Peter Y. K. Cheung
    A Tag Coprocessor Architecture for Symbolic Languages. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:370-373 [Conf]
  74. Salman Ahmed, Peter Y. K. Cheung
    Analog Fault Diagnosis - A Practical Approach. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:351-354 [Conf]
  75. Osama T. Albaharna, Peter Y. K. Cheung, Thomas J. Clarke
    Virtual Hardware and the Limits of Computational Speed-up. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:159-162 [Conf]
  76. Christos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung
    A novel 2D filter design methodology. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:532-535 [Conf]
  77. Nasir-ud-Din Gohar, Peter Y. K. Cheung
    A New Schematic-driven Floorplanning Algorithm for Analog Cell Layout. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1770-1773 [Conf]
  78. Akachai Sang-In, Peter Y. K. Cheung
    A Method of Representative Fault Selection in Digital Circuits for ATPG. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:73-76 [Conf]
  79. Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung
    Architectures for function evaluation on FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:804-807 [Conf]
  80. Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung
    A heuristic approach for multiple restricted multiplication. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:692-695 [Conf]
  81. Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk
    Multitasking in hardware-software codesign for reconfigurable computer. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:621-624 [Conf]
  82. Theerayod Wiangtong, Chun Te Ewe, Peter Y. K. Cheung
    SONICmole: a debugging environment for the UltraSONIC reconfigurable computer. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:808-811 [Conf]
  83. K. T. Tiew, A. J. Payne, Peter Y. K. Cheung
    MASH delta-sigma modulators for wideband and multi-standard applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:778-781 [Conf]
  84. Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk
    Autonomous Memory Block for reconfigurable computing. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:581-584 [Conf]
  85. Simon D. Haynes, John Stone, Peter Y. K. Cheung, Wayne Luk
    Video Image Processing with the Sonic Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2000, v:33, n:4, pp:50-57 [Journal]
  86. Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa
    Guest Editors' Introduction: Field Programmable Logic and Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:11, pp:1361-1362 [Journal]
  87. Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung
    A Gaussian Noise Generator for Hardware-Based Simulations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:12, pp:1523-1534 [Journal]
  88. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Wordlength optimization for linear digital signal processing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1432-1442 [Journal]
  89. Timo Koskinen, Peter Y. K. Cheung
    Hierarchical tolerance analysis using statistical behavioral models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:5, pp:506-516 [Journal]
  90. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Synthesis of saturation arithmetic architectures. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:3, pp:334-354 [Journal]
  91. Ray C. C. Cheung, N. J. Telle, Wayne Luk, Peter Y. K. Cheung
    Customizable elliptic curve cryptosystems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:9, pp:1048-1059 [Journal]
  92. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Optimum and heuristic synthesis of multiple word-length architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:39-57 [Journal]
  93. Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk
    Efficient Realtime FPGA Implementation of the Trace Transform. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  94. Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
    On-FPGA Communication Architectures and Design Factors. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-8 [Conf]
  95. Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
    Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  96. Sutjipto Arifin, Peter Y. K. Cheung
    Towards Affective Level Video Applications: A Novel FPGA-Based Video Arousal Content Modeling System. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  97. Christos-Savvas Bouganis, Peter Y. K. Cheung, Li Zhaoping
    FPGA-Accelerated Pre-Attentive Segmentation in Primary Visual Cortex. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  98. Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
    A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  99. Sutjipto Arifin, Peter Y. K. Cheung
    User Attention Based Arousal Content Modeling. [Citation Graph (0, 0)][DBLP]
    ICIP, 2006, pp:433-436 [Conf]
  100. Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung
    A Spatiotemporal Saliency Framework. [Citation Graph (0, 0)][DBLP]
    ICIP, 2006, pp:437-440 [Conf]
  101. Jonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides, Peter Y. K. Cheung
    Fast word-level power models for synthesis of FPGA-based arithmetic. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  102. Sutjipto Arifin, Peter Y. K. Cheung
    A computation method for video segmentation utilizing the pleasure-arousal-dominance emotional information. [Citation Graph (0, 0)][DBLP]
    ACM Multimedia, 2007, pp:68-77 [Conf]
  103. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
    On-Chip Communication in Run-Time Assembled Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:168-176 [Conf]
  104. Su-Shin Ang, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    A Flexible Multi-port Caching Scheme for Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:205-216 [Conf]
  105. Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, K. P. Lam
    A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:173-182 [Conf]
  106. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
    Run-Time Integration of Reconfigurable Video Processing Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:9, pp:1003-1016 [Journal]

  107. Bridging the Gap between FPGAs and Multi-Processor Architectures: A Video Processing Perspective. [Citation Graph (, )][DBLP]


  108. A DP-network for optimal dynamic routing in network-on-chip. [Citation Graph (, )][DBLP]


  109. Using Reconfigurable Logic to Optimise GPU Memory Accesses. [Citation Graph (, )][DBLP]


  110. Improved diagnosis of realistic interconnect shorts. [Citation Graph (, )][DBLP]


  111. Partition-based exploration for reconfigurable JPEG designs. [Citation Graph (, )][DBLP]


  112. Exploration of hardware sharing for image encoders. [Citation Graph (, )][DBLP]


  113. Automatic On-chip Memory Minimization for Data Reuse. [Citation Graph (, )][DBLP]


  114. A Hybrid Memory Sub-system for Video Coding Applications. [Citation Graph (, )][DBLP]


  115. Efficient Mapping of Dimensionality Reduction Designs onto Heterogeneous FPGAs. [Citation Graph (, )][DBLP]


  116. Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration. [Citation Graph (, )][DBLP]


  117. Benchmarking Reconfigurable Architectures in the Mobile Domain. [Citation Graph (, )][DBLP]


  118. Measuring and modeling FPGA clock variability. [Citation Graph (, )][DBLP]


  119. High-throughput interconnect wave-pipelining for global communication in FPGAs. [Citation Graph (, )][DBLP]


  120. Degradation in FPGAs: measurement and modelling. [Citation Graph (, )][DBLP]


  121. On the feasibility of early routing capacitance estimation for FPGAs. [Citation Graph (, )][DBLP]


  122. Efficient mapping of a Kalman filter into an FPGA using Taylor Expansion. [Citation Graph (, )][DBLP]


  123. Area estimation and optimisation of FPGA routing fabrics. [Citation Graph (, )][DBLP]


  124. Combating process variation on FPGAS with a precise at-speed delay measurement method. [Citation Graph (, )][DBLP]


  125. Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework. [Citation Graph (, )][DBLP]


  126. Towards benchmarking energy efficiency of reconfigurable architectures. [Citation Graph (, )][DBLP]


  127. Fault tolerant methods for reliability in FPGAs. [Citation Graph (, )][DBLP]


  128. Compensating for variability in FPGAs by re-mapping and re-placement. [Citation Graph (, )][DBLP]


  129. A Novel Video Parsing Algorithm Utilizing the Pleasure-Arousal-Dominance Emotional Information. [Citation Graph (, )][DBLP]


  130. Video enhancement on an adaptive image sensor. [Citation Graph (, )][DBLP]


  131. A sensor-based approach to linear blur identification for real-time video enhancement. [Citation Graph (, )][DBLP]


  132. Glitch-aware output switching activity from word-level statistics. [Citation Graph (, )][DBLP]


  133. Characterisation of FPGA Clock Variability. [Citation Graph (, )][DBLP]


  134. Systematic design space exploration for customisable multi-processor architectures. [Citation Graph (, )][DBLP]


  135. Interconnection lengths and delays estimation for communication links in FPGAs. [Citation Graph (, )][DBLP]


  136. Global interconnections in FPGAs: modeling and performance analysis. [Citation Graph (, )][DBLP]


  137. FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor. [Citation Graph (, )][DBLP]


  138. Parametric Design for Reconfigurable Software-Defined Radio. [Citation Graph (, )][DBLP]


  139. Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep. [Citation Graph (, )][DBLP]


  140. Process Variability and Degradation: New Frontier for Reconfigurable. [Citation Graph (, )][DBLP]


  141. Implementation of Wave-Pipelined Interconnects in FPGAs. [Citation Graph (, )][DBLP]


  142. Combining goal-directed, reactive and reflexive navigation in autonomous mobile robots. [Citation Graph (, )][DBLP]


  143. An incremental machine learning mechanism applied to robot navigation. [Citation Graph (, )][DBLP]


  144. A Novel Probabilistic Approach to Modeling the Pleasure-Arousal-Dominance Content of the Video based on "Working Memory". [Citation Graph (, )][DBLP]


  145. Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation. [Citation Graph (, )][DBLP]


  146. Comments on the BCS Lecture "The Future of Computer Technology and its Implications for the Computer Industry" by Professor Steve Furber. [Citation Graph (, )][DBLP]


Search in 0.001secs, Finished in 0.006secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002