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Stanislaw J. Piestrak: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Stanislaw J. Piestrak
    Membership Test Logic for Delay-Insensitive Codes. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:194-0 [Conf]
  2. Stanislaw J. Piestrak
    Feasibility Study of Designing TSC Sequential Circuits with 100% Fault Coverage. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:354-364 [Conf]
  3. Stanislaw J. Piestrak
    Design of encoders and self-testing checkers for some systematic unidirectional error detecting codes. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:119-127 [Conf]
  4. Stanislaw J. Piestrak, Abbas Dandache, Fabrice Monteiro
    Design of Fault-Secure Encoders for a Class of Systematic Error Correcting Codes. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:314-0 [Conf]
  5. Jerzy W. Greblicki, Stanislaw J. Piestrak
    Design of Totally Self-Checking Code-Disjoint Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    EDCC, 1999, pp:251-266 [Conf]
  6. Stanislaw J. Piestrak, Takashi Nanya
    Towards Totally Self-Checking Delay-Insensitive Systems. [Citation Graph (0, 0)][DBLP]
    FTCS, 1995, pp:228-237 [Conf]
  7. Stanislaw J. Piestrak
    Design of a Self-Testing Checker for Borden Code. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:582-585 [Conf]
  8. Stanislaw J. Piestrak
    Design of TSC Code-Disjoint Inverter-Free PLA's for Separable Unordered Codes. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:128-131 [Conf]
  9. Stanislaw J. Piestrak
    Design of High-Speed Residue-to-Binary Number System Converter Based on Chinese Remainder Theorem. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:508-511 [Conf]
  10. Stanislaw J. Piestrak
    Efficient Encoding? Decoding Circuitry for Systematic Unidirectional Error-Detecting Codes. [Citation Graph (0, 0)][DBLP]
    Fault-Tolerant Computing Systems, 1991, pp:181-192 [Conf]
  11. Stanislaw J. Piestrak, Dimitris Bakalis, Xrysovalantis Kavousianos
    On the Design of Self-Testing Checkers for Modified Berger Codes. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:153-157 [Conf]
  12. Damien Leroy, Stanislaw J. Piestrak, Fabrice Monteiro, Abbas Dandache
    Modeling of Transients Caused by a Laser Attack on Smart Cards. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:193-194 [Conf]
  13. Damien Leroy, Stanislaw J. Piestrak, Fabrice Monteiro, Abbas Dandache, Stéphane Rossignol, Pascal Moitrel
    Characterizing Laser-Induced Pulses in ICs: Methodology and Results. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:11-16 [Conf]
  14. Stanislaw J. Piestrak
    Self-Checking Design in Eastern Europe. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:1, pp:16-25 [Journal]
  15. Stanislaw J. Piestrak
    Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:2, pp:229-234 [Journal]
  16. Stanislaw J. Piestrak
    Comments on 'Novel Totally Self-Checking Berger Checker Designs Based on Generalized Berger Code Partitioning'. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:6, pp:735-736 [Journal]
  17. Stanislaw J. Piestrak
    Design of Fast Self-Testing Checkers for a Class of Berger Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:5, pp:629-634 [Journal]
  18. Stanislaw J. Piestrak
    Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:3, pp:360-374 [Journal]
  19. Stanislaw J. Piestrak
    The Minimal Test Set for Multioutput Threshold Circuits Implemented as Sorting Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:6, pp:700-712 [Journal]
  20. Stanislaw J. Piestrak
    Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:1, pp:68-77 [Journal]
  21. Stanislaw J. Piestrak
    Design of Self-Testing Checkers for Borden Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:4, pp:461-469 [Journal]
  22. Fabrice Monteiro, Stanislaw J. Piestrak, Houssein Jaber, Abbas Dandache
    Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:199-200 [Conf]
  23. Stanislaw J. Piestrak, Abbas Dandache, Fabrice Monteiro
    Designing fault-secure parallel encoders for systematic linear error correcting codes. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2003, v:52, n:4, pp:492-500 [Journal]
  24. Stanislaw J. Piestrak
    Design of minimal-level PLA self-testing checkers for m-out-of-n codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:264-272 [Journal]

  25. Exploiting residue number system for power-efficient digital signal processing in embedded processors. [Citation Graph (, )][DBLP]


  26. Design of a fault-tolerant coarse-grained. [Citation Graph (, )][DBLP]


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