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Juha Plosila: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Juha Plosila, Kaisa Sere
    Action Systems in Pipelined Processor Design. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1997, pp:156-166 [Conf]
  2. Tiberiu Seceleanu, Juha Plosila
    Formal Pipeline Design. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:167-172 [Conf]
  3. Juha Plosila, Kaisa Sere, Marina A. Waldén
    Design with Asynchronously Communicating Components. [Citation Graph (0, 0)][DBLP]
    FMCO, 2002, pp:424-442 [Conf]
  4. Tomi Westerlund, Juha Plosila
    Time Aware Modelling and Analysis of Multiclocked VLSI Systems. [Citation Graph (0, 0)][DBLP]
    ICFEM, 2006, pp:737-756 [Conf]
  5. Juha Plosila, Pasi Liljeberg, Jouni Isoaho
    Modelling and Refinement of an On-Chip Communication Architecture. [Citation Graph (0, 0)][DBLP]
    ICFEM, 2005, pp:219-234 [Conf]
  6. Juha Plosila, Tiberiu Seceleanu
    Specification of an Asynchronous On-chip Bus. [Citation Graph (0, 0)][DBLP]
    ICFEM, 2002, pp:383-395 [Conf]
  7. Tiberiu Seceleanu, Juha Plosila
    Constituent Elements of a Correctness-Preserving UML Design Approach. [Citation Graph (0, 0)][DBLP]
    IFM, 2004, pp:227-246 [Conf]
  8. Pasi Liljeberg, Juha Plosila, Jouni Isoaho
    Asynchronous interface for locally clocked modules in ULSI systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:170-173 [Conf]
  9. Pasi Liljeberg, Imed Ben Dhaou, Juha Plosila, Jouni Isoaho, Hannu Tenhunen
    Interconnect peak current reduction for wavelet array processor using self-timed signaling. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:485-488 [Conf]
  10. Ethiopia Nigussie, Juha Plosila, Jouni Isoaho
    Delay-Insensitive On-Chip Communication Link using Low-Swing Simultaneous Bidirectional Signaling. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:217-224 [Conf]
  11. Zheng Liang, Juha Plosila, Lu Yan, Kaisa Sere
    On-chip Debug for an Asynchronous Java Accelerator. [Citation Graph (0, 0)][DBLP]
    PDCAT, 2005, pp:312-315 [Conf]
  12. Zheng Liang, Juha Plosila, Lu Yan, Kaisa Sere
    Implementing a Self-Timed Low-Power Java Accelerator for Network-on-Chip Applications. [Citation Graph (0, 0)][DBLP]
    PDCAT, 2006, pp:344-347 [Conf]
  13. Tomi Westerlund, Juha Plosila
    Formal Specification of a Protocol Processor. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:122-131 [Conf]
  14. Juha Plosila, Tiberiu Seceleanu
    Design of Synchronous Action Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:578-583 [Conf]
  15. Juha Plosila, Tiberiu Seceleanu, Pasi Liljeberg
    Implementation of a Self-Timed Segmented Bus. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:6, pp:44-50 [Journal]
  16. Pasi Liljeberg, Juha Plosila, Jouni Isoaho
    Self-timed communication platform for implementing high-performance systems-on-chip. [Citation Graph (0, 0)][DBLP]
    Integration, 2004, v:38, n:1, pp:43-67 [Journal]
  17. Juha Plosila, Kaisa Sere, Marina A. Waldén
    Asynchronous system synthesis. [Citation Graph (0, 0)][DBLP]
    Sci. Comput. Program., 2005, v:55, n:1-3, pp:259-288 [Journal]
  18. Teijo Lehtonen, Pasi Liljeberg, Juha Plosila
    Fault Tolerance Analysis of NoC Architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:361-364 [Conf]
  19. Ethiopia Nigussie, Juha Plosila, Jouni Isoaho
    Current Mode On-Chip Interconnect using Level-Encoded Two-Phase Dual-Rail Encoding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:649-652 [Conf]
  20. Ethiopia Nigussie, Juha Plosila, Jouni Isoaho
    Full-duplex link implementation using dual-rail encoding and multiple-valued current-mode logic. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  21. Teijo Lehtonen, P. Rantala, P. Isomaki, Juha Plosila, Jouni Isoaho
    An approach for analysing and improving fault tolerance in radio architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  22. Tomi Westerlund, Juha Plosila
    Time Aware System Refinement. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2007, v:187, n:, pp:91-106 [Journal]

  23. Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs. [Citation Graph (, )][DBLP]


  24. An efficent dynamic multicast routing protocol for distributing traffic in NOCs. [Citation Graph (, )][DBLP]


  25. Self-timed thermal sensing and monitoring of multicore systems. [Citation Graph (, )][DBLP]


  26. Rigorous Communication Modelling at Transaction Level With Systemc. [Citation Graph (, )][DBLP]


  27. A novel hardware acceleration scheme for java method calls. [Citation Graph (, )][DBLP]


  28. Process variation tolerant on-chip communication using receiver and driver reconfiguration. [Citation Graph (, )][DBLP]


  29. A High-Performance Network Interface Architecture for NoCs Using Reorder Buffer Sharing. [Citation Graph (, )][DBLP]


  30. A Low-Latency and Memory-Efficient On-chip Network. [Citation Graph (, )][DBLP]


  31. Area efficient delay-insensitive and differential current sensing on-chip interconnect. [Citation Graph (, )][DBLP]


  32. Power Aware System Refinement. [Citation Graph (, )][DBLP]


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