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Cherrice Traver: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Robert B. Reese, Mitchell A. Thornton, Cherrice Traver
    A Coarse-Grain Phased Logic CPU. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:2-13 [Conf]
  2. Mitchell A. Thornton, Kenneth Fazel, Robert B. Reese, Cherrice Traver
    Generalized Early Evaluation in Self-Timed Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:255-259 [Conf]
  3. Garth Baulch, David Hemmendinger, Cherrice Traver
    Analyzing and verifying locally clocked circuits with the concurrency workbench. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:144-147 [Conf]
  4. Kenneth Fazel, Lun Li, Mitchell A. Thornton, Robert B. Reese, Cherrice Traver
    Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:413-416 [Conf]
  5. Richard Auletta, Robert B. Reese, Cherrice Traver
    A Comparison of Synchronous and Asynchronous FSMD Designs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:178-182 [Conf]
  6. Robert B. Reese, Mitchell A. Thornton, Cherrice Traver
    Arithmetic Logic Circuits Using Self-Timed Bit Level Dataflow and Early Evaluation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:18-23 [Conf]
  7. Robert B. Reese, Mitchell A. Thornton, Cherrice Traver
    A Fine-Grain Phased Logic CPU. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:70-79 [Conf]
  8. Robert B. Reese, Mitchell A. Thornton, Cherrice Traver
    A Coarse-Grain Phased Logic CPU. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:7, pp:788-799 [Journal]
  9. Robert B. Reese, Mitchell A. Thornton, Cherrice Traver, David Hemmendinger
    Early evaluation for performance enhancement in phased logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:532-550 [Journal]
  10. K. W. Hsu, Cherrice Traver
    Guest Editorial Introduction to the Special Issue on the 1995 IEEE ASIC Conference. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:3, pp:305- [Journal]

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