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Publications of Author

1. J. W. J. M. Rutten, Michel R. C. M. Berkelaar
   Improved State Assignment for Burst Mode Finite State Machines. [Citation Graph (0, 0)][DBLP]
   ASYNC, 1997, pp:228-239 [Conf]
   
2. Michel R. C. M. Berkelaar, Koen van Eijk
   Efficient and Effective Redundancy Removal for Million-Gate Circuits. [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:1088- [Conf]
   
3. E. T. A. F. Jacobs, Michel R. C. M. Berkelaar
   Gate Sizing Using a Statistical Delay Model. [Citation Graph (0, 0)][DBLP]
   DATE, 2000, pp:283-0 [Conf]
   
4. J. W. J. M. Rutten, Michel R. C. M. Berkelaar, C. A. J. van Eijk, M. A. J. Kolsteren
   An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization. [Citation Graph (0, 0)][DBLP]
   DATE, 1998, pp:749-754 [Conf]
   
5. Harm Arts, Michel R. C. M. Berkelaar, C. A. J. van Eijk
   Polarized observability don't cares. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1996, pp:626-631 [Conf]
   
6. Reinaldo A. Bergamaschi, Daniel Brand, Leon Stok, Michel R. C. M. Berkelaar, S. Prakash
   Efficient use of large don't cares in high-level and logic synthesis. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1995, pp:272-278 [Conf]
   
7. Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess
   Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1994, pp:474-480 [Conf]
   
8. Michel R. C. M. Berkelaar, Lukas P. P. P. van Ginneken
   Efficient orthonormality testing for synthesis with pass-transistor selectors. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1995, pp:256-263 [Conf]
   
9. Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz
   Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning. [Citation Graph (0, 0)][DBLP]
   ICCD, 2004, pp:350-353 [Conf]
   
10. Harm Arts, Michel R. C. M. Berkelaar, Koen van Eijk
    Computing observability don't cares efficiently through polarization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:7, pp:573-581 [Journal]
    
11. Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess
    Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:11, pp:1424-1434 [Journal]
    
12. 
    Gate sizing in MOS digital circuits with linear programming. [Citation Graph (, )][DBLP]