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Peter R. Wilson: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mathew A. Sacker, Andrew D. Brown, Peter R. Wilson, Andrew J. Rushton
    A General Purpose Behavioural Asynchronous Synthesis System. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:125-134 [Conf]
  2. Peter R. Wilson, J. Neil Ross, Andrew D. Brown, Tom J. Kazmierski, Jerzy Baranowski
    Efficient Mixed-Domain Behavioural Modeling of Ferromagnetic Hysteresis Implemented in VHDL-AMS. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:742-743 [Conf]
  3. Peter R. Wilson, J. Neil Ross, Mark Zwolinski, Andrew D. Brown, Yavuz Kiliç
    Behavioural Modelling of Operational Amplifier Faults Using VHDL-AMS. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1133- [Conf]
  4. Peter R. Wilson
    A view of STEP. [Citation Graph (0, 0)][DBLP]
    Geometric Modeling, 1992, pp:267-296 [Conf]
  5. Peter R. Wilson
    A note on curve equality. [Citation Graph (0, 0)][DBLP]
    Geometric Modeling, 1992, pp:321-325 [Conf]
  6. Peter R. Wilson, J. Neil Ross, Andrew D. Brown, Andrew J. Rushton
    Multiple domain behavioral modeling using VHDL-AMS. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:644-647 [Conf]
  7. Peter Wilson, Reuben Wilcock
    Behavioural modeling and simulation of a switched-current phase locked loop. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5174-5177 [Conf]
  8. Peter Wilson, Reuben Wilcock, Bashir M. Al-Hashimi
    A novel switched-current phase locked loop. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2815-2818 [Conf]
  9. Peter R. Wilson
    EUG'91 Meeting Notes. [Citation Graph (0, 0)][DBLP]
    SIGMOD Record, 1992, v:21, n:1, pp:90-92 [Journal]
  10. Mathew A. Sacker, Andrew D. Brown, Andrew J. Rushton, Peter R. Wilson
    A behavioral synthesis system for asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:9, pp:978-994 [Journal]
  11. S. S. Modi, P. R. Wilson, A. D. Brown
    Power aware learning for class AB analogue VLSI neural network. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  12. A communication infrastructure for a million processor machine. [Citation Graph (, )][DBLP]


  13. A New Approach for Combining Yield and Performance in Behavioural Models for Analogue Integrated Circuits. [Citation Graph (, )][DBLP]


  14. SpiNNaker: The Design Automation Problem. [Citation Graph (, )][DBLP]


  15. Improved 6.7GHz CMOS VCO delay cell with up to seven octave tuning range. [Citation Graph (, )][DBLP]


  16. Advanced Encryption Standard (AES) implementation with increased DPA resistance and low overhead. [Citation Graph (, )][DBLP]


  17. A novel approach to mixed-domain behavioral modeling of ferromagnetic hysteresis in VHDL-AMS. [Citation Graph (, )][DBLP]


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