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Publications of Author

1. Andrew M. Scott, Mark E. Schuelein, Marly Roncken, Jin-Jer Hwan, John Bainbridge, John R. Mawer, David L. Jackson, Andrew Bardsley
   Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2007, pp:60-72 [Conf]
   
2. Aristides Efthymiou, John Bainbridge, Douglas A. Edwards
   Adding Testability to an Asynchronous Interconnect for GALS SoC. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2004, pp:20-23 [Conf]
   
3. John Bainbridge, R. W. Whitty, John Wordsworth
   Obtaining Structural Metrics of Z Specifications for Systems Development. [Citation Graph (0, 0)][DBLP]
   Z User Workshop, 1990, pp:269-281 [Conf]
   
4. John Bainbridge
   A Heuristic Method for Generating Large Random Expressions. [Citation Graph (0, 0)][DBLP]
   Inf. Process. Lett., 1992, v:44, n:3, pp:165-170 [Journal]
   
5. John Bainbridge, Stephen B. Furber
   Chain: A Delay-Insensitive Chip Area Interconnect. [Citation Graph (0, 0)][DBLP]
   IEEE Micro, 2002, v:22, n:5, pp:16-23 [Journal]
   
6. Stephen B. Furber, John Bainbridge, J. Mike Cumpstey, Steve Temple
   Sparse distributed memory using N-of-M codes. [Citation Graph (0, 0)][DBLP]
   Neural Networks, 2004, v:17, n:10, pp:1437-1451 [Journal]
   
7. John Bainbridge
   Defining Testability Metrics Axiomatically. [Citation Graph (0, 0)][DBLP]
   Softw. Test., Verif. Reliab., 1994, v:4, n:2, pp:63-80 [Journal]
   
8. Aristides Efthymiou, John Bainbridge, Douglas A. Edwards
   Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:12, pp:1384-1393 [Journal]
   
9. 
   An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator. [Citation Graph (, )][DBLP]