The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Yoshiki Saito: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author


  1. Cache Controller Design on Ultra Low Leakage Embedded Processors. [Citation Graph (, )][DBLP]


  2. Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors. [Citation Graph (, )][DBLP]


  3. A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array. [Citation Graph (, )][DBLP]


  4. Power reduction techniques for Dynamically Reconfigurable Processor Arrays. [Citation Graph (, )][DBLP]


  5. Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors. [Citation Graph (, )][DBLP]


Search in 0.001secs, Finished in 0.001secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002