The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Yangyang Pan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author


  1. Improving VLIW Processor Performance Using Three-Dimensional (3D) DRAM Stacking. [Citation Graph (, )][DBLP]


  2. DRAM-based FPGA enabled by three-dimensional (3d) memory stacking (abstract only). [Citation Graph (, )][DBLP]


Search in 0.027secs, Finished in 0.027secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002