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Publications of Author

1. Nagu R. Dhanwada, Ing-Chao Lin, Vijay Narayanan
   A power estimation methodology for systemC transaction level models. [Citation Graph (0, 0)][DBLP]
   CODES+ISSS, 2005, pp:142-147 [Conf]
   
2. Yuh-Fang Tsai, Vijaykrishnan Narayaynan, Yuan Xie, Mary Jane Irwin
   Leakage-Aware Interconnect for On-Chip Network [Citation Graph (0, 0)][DBLP]
   CoRR, 2007, v:0, n:, pp:- [Journal]
   
3. 
   A criticality-driven microarchitectural three dimensional (3D) floorplanner. [Citation Graph (, )][DBLP]
   
   
4. 
   Reliability-aware design for nanometer-scale devices. [Citation Graph (, )][DBLP]
   
   
5. 
   A Hardware Efficient Support Vector Machine Architecture for FPGA. [Citation Graph (, )][DBLP]
   
   
6. 
   A Unified Streaming Architecture for Real Time Face Detection and Gender Classification. [Citation Graph (, )][DBLP]
   
   
7. 
   TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platforms. [Citation Graph (, )][DBLP]
   
   
8. 
   A low-power phase change memory based hybrid cache architecture. [Citation Graph (, )][DBLP]
   
   
9. 
   In-Network Caching for Chip Multiprocessors. [Citation Graph (, )][DBLP]
   
   
10. 
    Performance and power optimization through data compression in Network-on-Chip architectures. [Citation Graph (, )][DBLP]
    
    
11. 
    Thermal-aware reliability analysis for platform FPGAs. [Citation Graph (, )][DBLP]
    
    
12. 
    Green transistors to green architectures. [Citation Graph (, )][DBLP]
    
    
13. 
    Security and Dependability of Embedded Systems: A Computer Architects' Perspective. [Citation Graph (, )][DBLP]
    
    
14. 
    Analyzing Energy-Delay Behavior in Room Temperature Single Electron Transistors. [Citation Graph (, )][DBLP]
    
    
15. 
    Efficient Function Evaluations with Lookup Tables for Structured Matrix Operations. [Citation Graph (, )][DBLP]
    
    
16. 
    Efficient image reconstruction using partial 2D Fourier transform. [Citation Graph (, )][DBLP]
    
    
17. 
    FPGA architecture for 2D Discrete Fourier Transform based on 2D decomposition for large-sized data. [Citation Graph (, )][DBLP]
    
    
18. 
    Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors. [Citation Graph (, )][DBLP]