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Publications of Author

1. D. P. Vasudevan, Parag K. Lala, James Patrick Parkerson
   A Novel Approach for On-line Testable Reversible Logic Circuit Desig. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2004, pp:325-330 [Conf]
   
2. D. P. Vasudevan, Parag K. Lala
   A New Reversible Logic Gate and its Applications. [Citation Graph (0, 0)][DBLP]
   ESA/VLSI, 2004, pp:480-484 [Conf]
   
3. Jia Di, D. P. Vasudevan
   Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays. [Citation Graph (0, 0)][DBLP]
   DELTA, 2006, pp:149-156 [Conf]
   
4. Jia Di, Parag K. Lala, D. P. Vasudevan
   On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits. [Citation Graph (0, 0)][DBLP]
   DFT, 2005, pp:371-379 [Conf]
   
5. D. P. Vasudevan, Parag K. Lala
   A Technique for Modular Design of Self-Checking Carry-Select Adder. [Citation Graph (0, 0)][DBLP]
   DFT, 2005, pp:325-333 [Conf]
   
6. D. P. Vasudevan, Parag K. Lala, James Patrick Parkerson
   Online Testable Reversible Logic Circuit Design using NAND Blocks. [Citation Graph (0, 0)][DBLP]
   DFT, 2004, pp:324-331 [Conf]
   
7. D. P. Vasudevan, Parag K. Lala, James Patrick Parkerson
   CMOS Realization of Online Testable Reversible Logic Gates. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2005, pp:309-310 [Conf]
   
8. D. P. Vasudevan, James Patrick Parkerson, Parag K. Lala
   Logic implementation using a reversible gate. [Citation Graph (0, 0)][DBLP]
   Circuits, Signals, and Systems, 2004, pp:452-456 [Conf]
   
9. 
   Reversible online BIST using bidirectional BILBO. [Citation Graph (, )][DBLP]
   
   
10. 
    A Partial Scan Based Test Generation for Asynchronous Circuits. [Citation Graph (, )][DBLP]