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Publications of Author

1. 
   New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults. [Citation Graph (, )][DBLP]
   
   
2. 
   Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints. [Citation Graph (, )][DBLP]
   
   
3. 
   Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs. [Citation Graph (, )][DBLP]
   
   
4. 
   Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip. [Citation Graph (, )][DBLP]
   
   
5. 
   Reconfigurable Multithreading Architectures: A Survey. [Citation Graph (, )][DBLP]
   
   
6. 
   Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints. [Citation Graph (, )][DBLP]