The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Suresh Chalasani: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Fotios K. Liotopoulos, Suresh Chalasani
    Semi-centralized routing algorithm for 3-stage Clos networks. [Citation Graph (0, 0)][DBLP]
    Modelling and Evaluation of ATM Networks, 1994, pp:147-176 [Conf]
  2. Fotios K. Liotopoulos, Suresh Chalasani
    Strictly nonblocking operation of 3-stage Clos switching networks. [Citation Graph (0, 0)][DBLP]
    Modelling and Evaluation of ATM Networks, 1995, pp:269-286 [Conf]
  3. Suresh Chalasani, Rajendra V. Boppana
    Communication in Multicomputers with Nonconvex Faults. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1995, pp:673-684 [Conf]
  4. Rajendra V. Boppana, Rajesh Boppana, Suresh Chalasani
    Designing SANs to Support Low-Fanout Multicasts. [Citation Graph (0, 0)][DBLP]
    HiPC, 2003, pp:217-227 [Conf]
  5. Suresh Chalasani, Rajendra V. Boppana
    Fault-Tolerance with Multimodule Routers. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:201-210 [Conf]
  6. Suresh Chalasani, Parameswaran Ramanathan
    Parallel FFT on ATM-based Networks of Workstations. [Citation Graph (0, 0)][DBLP]
    HPDC, 1997, pp:2-11 [Conf]
  7. James Puthukattukaran, Suresh Chalasani, Periannan Senapathy
    Design and Implementation of Parallel Algorithms for Gene-Finding. [Citation Graph (0, 0)][DBLP]
    HPDC, 1994, pp:186-193 [Conf]
  8. Rajendra V. Boppana, Suresh Chalasani
    Fault-Tolerant Multicast Communication for Multicomputers. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1995, pp:118-125 [Conf]
  9. Monika ten Bruggencate, Suresh Chalasani
    Equivalence Between SP2 High-Performance Switches and Three-Stage CLOS Networks. [Citation Graph (0, 0)][DBLP]
    ICPP, Vol. 1, 1996, pp:1-8 [Conf]
  10. Suresh Chalasani, Anujan Varma
    Fast Parallel Time-Slot Assignment Algorithms for TDM Switching Systems. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1990, pp:154-161 [Conf]
  11. Fotios K. Liotopoulos, Suresh Chalasani
    Nonblocking Operation of Asymmetrical Clos Networks. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1994, pp:101-108 [Conf]
  12. Parameswaran Ramanathan, Suresh Chalasani
    Resource Placement in k-Ary n-Cubes. [Citation Graph (0, 0)][DBLP]
    ICPP (2), 1992, pp:133-140 [Conf]
  13. Suresh Chalasani, Rajendra V. Boppana
    Fault-tolerant wormhole routing in tori. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1994, pp:146-155 [Conf]
  14. Suresh Chalasani, Anujan Varma
    Efficient Time-Slot Assignment Algorithms for SS/TDMA Systems with Variable-Bandwidth Beams. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 1991, pp:658-667 [Conf]
  15. Anujan Varma, Suresh Chalasani
    Reduction of Crosspoints in One-Sided Crosspoint Switching Networks. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 1989, pp:943-952 [Conf]
  16. Rajendra V. Boppana, Suresh Chalasani
    New Wormhole Routing Algorithms for Multicomputers. [Citation Graph (0, 0)][DBLP]
    IPPS, 1993, pp:419-423 [Conf]
  17. Gebre A. Gessesse, Suresh Chalasani
    New Degree Four Networks: Properties and Performance. [Citation Graph (0, 0)][DBLP]
    IPPS, 1993, pp:168-172 [Conf]
  18. C. S. Raghavendra, Suresh Chalasani, Rajendra V. Boppana
    Improved Algorithms for Load Balancing in Circuit-Switched Hypercubes. [Citation Graph (0, 0)][DBLP]
    IPPS, 1991, pp:537-542 [Conf]
  19. Anujan Varma, Suresh Chalasani
    Asymmetrical Multiconnection Three-Stage Clos Networks. [Citation Graph (0, 0)][DBLP]
    IPPS, 1992, pp:411-414 [Conf]
  20. Rajendra V. Boppana, Suresh Chalasani
    A Comparison of Adaptive Wormhole Routing Algorithms. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:351-360 [Conf]
  21. Suresh Chalasani, Rajendra V. Boppana
    Software Architectures for E-Commerce Computing Systems with External Hosting. [Citation Graph (0, 0)][DBLP]
    ITCC, 2002, pp:504-511 [Conf]
  22. Suresh Chalasani, Anujan Varma
    Analysis and Simalation of Multistage Interconnection Networks under Non-Uniform Traffic. [Citation Graph (0, 0)][DBLP]
    PARBASE / Architectures, 1990, pp:68-87 [Conf]
  23. Rajendra V. Boppana, Suresh Chalasani
    Fault-tolerant routing with non-adaptive wormhole algorithms in mesh networks. [Citation Graph (0, 0)][DBLP]
    SC, 1994, pp:693-702 [Conf]
  24. Monika ten Bruggencate, Suresh Chalasani
    Parallel Implementations of the Power System Transient Stability Problem on Clusters of Workstations. [Citation Graph (0, 0)][DBLP]
    SC, 1995, pp:- [Conf]
  25. Suresh Chalasani, Anujan Varma, C. S. Raghavendra
    Fault-tolerant routing in MIN-based supercomputers. [Citation Graph (0, 0)][DBLP]
    SC, 1990, pp:244-253 [Conf]
  26. Suresh Chalasani, Parameswaran Ramanathan
    Parallel FFT on ATM-based networks of workstations. [Citation Graph (0, 0)][DBLP]
    Cluster Computing, 1998, v:1, n:1, pp:13-26 [Journal]
  27. Suresh Chalasani, Rajendra V. Boppana
    Adaptive Multimodule Routers for Multiprocessor Architectures. [Citation Graph (0, 0)][DBLP]
    Information Systems Frontiers, 2005, v:7, n:3, pp:317-327 [Journal]
  28. Suresh Chalasani, C. S. Raghavendra, Anujan Varma
    Fault-Tolerant Routing in MIN-Based Supercomputers. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1994, v:22, n:2, pp:154-167 [Journal]
  29. Ge-Ming Chiu, Suresh Chalasani, C. S. Raghavendra
    Flexible Routing Criteria for Circuit-Switched Hypercubes. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1994, v:22, n:2, pp:279-294 [Journal]
  30. Anujan Varma, Suresh Chalasani
    An Incremental Algorithm for TDM Switching Assignments in Satellite and Terrestrial Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Journal on Selected Areas in Communications, 1992, v:10, n:2, pp:364-377 [Journal]
  31. Rajendra V. Boppana, Suresh Chalasani
    Fault-Tolerant Wormhole Routing Algorithms for Mesh Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:7, pp:848-864 [Journal]
  32. Suresh Chalasani
    A New Parallel Algorithm for Time-Slot Assignment in Hierarchical Switching Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:12, pp:1387-1395 [Journal]
  33. Suresh Chalasani, Rajendra V. Boppana
    Communication in Multicomputers with Nonconvex Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:5, pp:616-622 [Journal]
  34. Anujan Varma, Suresh Chalasani
    Fault-Tolerance Analysis of One-Sided Crosspoint Switching Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:2, pp:143-158 [Journal]
  35. Fotios K. Liotopoulos, Suresh Chalasani
    Semi-rearrangeably nonblocking operation of Clos networks in the multirate environment. [Citation Graph (0, 0)][DBLP]
    IEEE/ACM Trans. Netw., 1996, v:4, n:2, pp:281-291 [Journal]
  36. Rajendra V. Boppana, Suresh Chalasani
    A Framework for Designing Deadlock-Free Wormhole Routing Algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1996, v:7, n:2, pp:169-183 [Journal]
  37. Rajendra V. Boppana, Suresh Chalasani
    Fault-Tolerant Communication with Partitioned Dimension-Order Routers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1999, v:10, n:10, pp:1026-1039 [Journal]
  38. Rajendra V. Boppana, Suresh Chalasani, C. S. Raghavendra
    Resource Deadlocks and Performance of Wormhole Multicast Routing Algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1998, v:9, n:6, pp:535-549 [Journal]
  39. Suresh Chalasani, Anujan Varma
    Evaluation of Two Traffic Distribution Strategies for a Dual-Network Multiprocessor System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1992, v:3, n:3, pp:375-384 [Journal]
  40. Parameswaran Ramanathan, Suresh Chalasani
    Resource Placement with Multiple Adjacency Constraints in k-ary n-Cubes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1995, v:6, n:5, pp:511-519 [Journal]

  41. Flexible, fault-tolerant routing criteria for circuit-switched hypercubes. [Citation Graph (, )][DBLP]


Search in 0.033secs, Finished in 0.034secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002