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Hiroshi Date: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka
    A SoC Test Strategy Based on a Non-Scan DFT Method. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:305-310 [Conf]
  2. Hiroshi Date, Michinobu Nakao, Kazumi Hatayama
    A parallel sequential test generation system DESCARTES based on real-valued logic simulation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:252-258 [Conf]
  3. Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka
    A State Reduction Method for Non-Scan Based FSM Testing with Don't Care Inputs Identification Technique. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:55-60 [Conf]
  4. Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, Hideo Fujiwara
    A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:130-135 [Conf]
  5. Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara
    A DFT Selection Method for Reducing Test Application Time of System-on-Chips. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:412-417 [Conf]
  6. Makoto Sugihara, Hiroto Yasuura, Hiroshi Date
    Analysis and Minimization of Test Time in a Combined BIST and External Test Approach. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:134-140 [Conf]
  7. Hiroshi Date, Yukinori Matsumoto, Kouichi Kimura, Kazuo Taki, Hiroo Kato, Masahiro Hoshi
    LSI-CAD Programs on Parallel Inference Machine. [Citation Graph (0, 0)][DBLP]
    FGCS, 1992, pp:237-247 [Conf]
  8. Makoto Sugihara, Hiroshi Date, Hiroto Yasuura
    A novel test methodology for core-based system LSIs and a testing time minimization problem. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:465-0 [Conf]
  9. Hiroshi Date, Vikram Iyengar, Krishnendu Chakrabarty, Makoto Sugihara
    Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable Cores. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  10. Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka
    A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:328-335 [Conf]

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