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Michinobu Nakao: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hiroshi Date, Michinobu Nakao, Kazumi Hatayama
    A parallel sequential test generation system DESCARTES based on real-valued logic simulation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:252-258 [Conf]
  2. Kazumi Hatayama, Michinobu Nakao, Yasuo Sato
    At-Speed Built-in Test for Logic Circuits with Multiple Clocks. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:292-297 [Conf]
  3. Michinobu Nakao, Kazumi Hatayama, Isao Higashi
    Accelerated Test Points Selection Method for Scan-Based BIST. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:359-0 [Conf]
  4. Michinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo
    Test Generation for Multiple-Threshold Gate-Delay Fault Model. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:244-0 [Conf]
  5. Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo
    Application of High-Quality Built-In Test to Industrial Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1003-1012 [Conf]
  6. Michinobu Nakao, Seiji Kobayashi, Kazumi Hatayama, Kazuhiko Iijima, Seiji Terada
    Low overhead test point insertion for scan-based BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:348-357 [Conf]

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