Search the dblp DataBase

Publications of Author

1. Magdy S. Abadir, Jing Zeng, Carol Pyron, Juhong Zhu
   Automated Test Model Generation from Switch Level Custom Circuits. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2003, pp:184-189 [Conf]
   
2. Jing Zeng, Magdy S. Abadir, Jacob A. Abraham
   False timing path identification using ATPG techniques and delay-based information. [Citation Graph (0, 0)][DBLP]
   DAC, 2002, pp:562-565 [Conf]
   
3. Li-C. Wang, Magdy S. Abadir, Jing Zeng
   Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays. [Citation Graph (0, 0)][DBLP]
   DATE, 1998, pp:273-277 [Conf]
   
4. Jing Zeng, Magdy S. Abadir, Jayanta Bhadra, Jacob A. Abraham
   Full chip false timing path identification: applications to the PowerPCTM microprocessors. [Citation Graph (0, 0)][DBLP]
   DATE, 2001, pp:514-519 [Conf]
   
5. Jing Zeng, Magdy S. Abadir, A. Kolhatkar, G. Vandling, Li-C. Wang, Jacob A. Abraham
   On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. [Citation Graph (0, 0)][DBLP]
   ITC, 2004, pp:31-37 [Conf]
   
6. Jing Zeng, Magdy S. Abadir, G. Vandling, Li-C. Wang, S. Karako, Jacob A. Abraham
   On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. [Citation Graph (0, 0)][DBLP]
   MTV, 2004, pp:103-109 [Conf]
   
7. Li-C. Wang, Magdy S. Abadir, Jing Zeng
   On Logic and Transistor Level Design Error Detection of Various Validation Approaches for PowerPC(tm) Microprocessor Arrays. [Citation Graph (0, 0)][DBLP]
   VTS, 1998, pp:260-265 [Conf]
   
8. Li-C. Wang, Magdy S. Abadir, Jing Zeng
   On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:4, pp:524-532 [Journal]
   
9. 
   On evaluating speed path detection of structural tests. [Citation Graph (, )][DBLP]
   
   
10. 
    Scan based speed-path debug for a microprocessor. [Citation Graph (, )][DBLP]
    
    
11. 
    Reliability and Parametric Sensitivity Analysis of Railway Vehicle Bogie Frame Based on Monte-Carlo Numerical Simulation. [Citation Graph (, )][DBLP]