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Sying-Jyan Wang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yu-Hsuan Fu, Sying-Jyan Wang
    Test Data Compression with Partial LFSR-Reseeding. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:343-347 [Conf]
  2. Nan-Cheng Li, Sying-Jyan Wang
    A Reseeding Technique for LFSR-Based BIST Applications. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:200-205 [Conf]
  3. Po-Ching Hsu, Sying-Jyan Wang
    Testing And Diagnosis Of Board Interconnects In Microprocessor-Based Systems. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:56-61 [Conf]
  4. Nan-Cheng Lai, Sying-Jyan Wang, Yu-Hsuan Fu
    Low Power BIST with Smoother and Scan-Chain Reorder . [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:40-45 [Conf]
  5. Sying-Jyan Wang, Chao-Neng Huang
    Testing and Diagnosis of Interconnect Structures in FPGAs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:283-0 [Conf]
  6. Sying-Jyan Wang, Chen-Jung Wei
    Efficient built-in self-test algorithm for memory. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:66-0 [Conf]
  7. Sying-Jyan Wang, Sheng-Nan Chiou
    Generating Efficient Tests for Continuous Scan. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:162-165 [Conf]
  8. Sying-Jyan Wang
    Synthesis of Sequential Machines with Reduced Testing Cost. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:302-306 [Conf]
  9. Sying-Jyan Wang, Tsi-Ming Tsai
    Test and diagnosis of fault logic blocks in FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:722-727 [Conf]
  10. Niraj K. Jha, Sying-Jyan Wang
    Design and Synthesis of Self-Checking VLSI Circuits and Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:578-581 [Conf]
  11. Niraj K. Jha, Sying-Jyan Wang, Phillip C. Gripka
    Multiple Input Bridging Fault Detection in CMOS Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:369-372 [Conf]
  12. Ming-Chen Wen, Sying-Jyan Wang, Yen-Nan Lin
    Low power parallel multiplier with column bypassing. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1638-1641 [Conf]
  13. Yu-Lung Hsu, Sying-Jyan Wang
    Retiming-based logic synthesis for low-power. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:275-278 [Conf]
  14. Sying-Jyan Wang
    Distributed Routing in a Fault-Tolerant Multistage Interconnection Network. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1997, v:63, n:4, pp:205-210 [Journal]
  15. Sying-Jyan Wang, Chia-Chun Lien
    Testability Improvement by Branch Point Control for Conditional Staements With Multiple Branches. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2000, v:16, n:5, pp:719-731 [Journal]
  16. Sying-Jyan Wang
    Distributed Diagnosis in Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2001, v:61, n:2, pp:254-264 [Journal]
  17. Sying-Jyan Wang
    Load-Balancing in Multistage Interconnection Networks under Multiple-Pass Routing. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1996, v:36, n:2, pp:189-194 [Journal]
  18. Sying-Jyan Wang, Niraj K. Jha
    Algorithm-Based Fault Tolerance for FFT Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:7, pp:849-854 [Journal]
  19. Niraj K. Jha, Sying-Jyan Wang
    Design and synthesis of self-checking VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:6, pp:878-887 [Journal]
  20. Sying-Jyan Wang, Tung-Hua Yeh
    High-level test synthesis for delay fault testability. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:45-50 [Conf]
  21. Sying-Jyan Wang, Yan-Ting Chen, Katherine Shu-Min Li
    Low Capture Power Test Generation for Launch-off-Capture Transition Test Based on Don't-Care Filling. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3683-3686 [Conf]
  22. Po-Chang Tsai, Sying-Jyan Wang, Ching-Hung Lin, Tung-Hua Yeh
    Test Data Compression for Minimum Test Application Time. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2007, v:23, n:6, pp:1901-1909 [Journal]

  23. Design and analysis of skewed-distribution scan chain partition for improved test data compression. [Citation Graph (, )][DBLP]


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