The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Sandeep K. Gupta: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
    A new framework for static timing analysis, incremental timing refinement, and timing simulation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:102-107 [Conf]
  2. Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
    Test generation for crosstalk-induced faults: framework and computational result. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:305-310 [Conf]
  3. Chen-Huan Chiang, Sandeep K. Gupta
    BIST TPG for SRAM cluster interconnect testing at board level. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:58-65 [Conf]
  4. Chen-Huan Chiang, Sandeep K. Gupta
    BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:244-252 [Conf]
  5. Melvin A. Breuer, Sandeep K. Gupta, Shahin Nazarian
    Efficient Identification of Crosstalk Induced Slowdown Targets. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:124-131 [Conf]
  6. Yuan-Chieh Hsu, Sandeep K. Gupta
    An Automatic Test Pattern Generator for At-Speed Robust Path Delay Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:88-95 [Conf]
  7. I-De Huang, Sandeep K. Gupta
    Selection of Paths for Delay Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:208-215 [Conf]
  8. Zhigang Jiang, Sandeep K. Gupta
    A Test Generation Approach for Systems-on-Chip that Use Intellectual Property Cores. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:278-283 [Conf]
  9. Zhigang Jiang, Sandeep K. Gupta
    Threshold testing: Covering bridging and other realistic faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:390-397 [Conf]
  10. Md. Saffat Quasem, Sandeep K. Gupta
    Designing Multiple Scan Chains for Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:424-427 [Conf]
  11. Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
    An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:174-177 [Conf]
  12. Wichian Sirisaengtaksin, Sandeep K. Gupta
    Enhanced Crosstalk Fault Model and Methodology to Generate Tests for Arbitrary Inter-core Interconnect Topology. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:163-169 [Conf]
  13. Wichian Sirisaengtaksin, Sandeep K. Gupta
    Modeling and Testing Crosstalk Faults in Inter-Core Interconnects that Include Tri-State and Bi-Directional Nets. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:132-139 [Conf]
  14. Wichian Sirisaengtaksin, Sandeep K. Gupta
    A Methodology to Compute Bounds on Crosstalk Effects in Arbitrary Interconnects. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:112-119 [Conf]
  15. Lei Wang, Sandeep K. Gupta, Melvin A. Breuer
    Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip Interconnects. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:440-447 [Conf]
  16. Sandeep K. Gupta, John D. Kececioglu, Alejandro A. Schäffer
    Making the Shortest-Paths Approach to Sum-of-Pairs Multiple Sequence Alignment More Space Efficient in Practice (Extended Abstract). [Citation Graph (0, 0)][DBLP]
    CPM, 1995, pp:128-143 [Conf]
  17. Chih-Ang Chen, Sandeep K. Gupta
    A Satisfiability-Based Test Generator for Path Delay Faults in Combinational Circuts. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:209-214 [Conf]
  18. Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
    A New Gate Delay Model for Simultaneous Switching and Its Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:289-294 [Conf]
  19. Wen-Chang Fang, Sandeep K. Gupta
    Clock Grouping: A Low Cost DFT Methodology for Delay Testing. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:94-99 [Conf]
  20. Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
    Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:395-401 [Conf]
  21. Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
    Lower Bounds on Test Resources for Scheduled Data Flow Graphs. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:143-148 [Conf]
  22. Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
    Introducing Redundant Computations in a Behavior for Reducing BIST Resources. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:548-553 [Conf]
  23. Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer
    An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:242-248 [Conf]
  24. Seongmoon Wang, Sandeep K. Gupta
    ATPG for Heat Dissipation Minimization During Scan Testing. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:614-619 [Conf]
  25. Shahin Nazarian, Massoud Pedram, Sandeep K. Gupta, Melvin A. Breuer
    STAX: statistical crosstalk target set compaction. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:172-177 [Conf]
  26. Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
    Scheduling and Module Assignment for Reducing Bist Resources. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:66-73 [Conf]
  27. Md. Saffat Quasem, Sandeep K. Gupta
    Exact fault simulation for systems on Silicon that protects each core's intellectual property. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:804- [Conf]
  28. Suriyaprakash Natarajan, Melvin A. Breuer, Sandeep K. Gupta
    Process Variations and their Impact on Circuit Operation. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:73-0 [Conf]
  29. Sen-Pin Lin, Sandeep K. Gupta, Melvin A. Breuer
    A Low Cost BIST Methodology and Associated Novel Test Pattern Generator. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:106-112 [Conf]
  30. Chih-Ang Chen, Sandeep K. Gupta
    BIST Test Pattern Generators for Stuck-Open and Delay Testing. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:289-296 [Conf]
  31. Chen-Huan Chiang, Sandeep K. Gupta
    Random pattern testable logic synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:125-128 [Conf]
  32. Chen-Huan Chiang, Sandeep K. Gupta
    BIST TPG for faults in system backplanes. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:406-413 [Conf]
  33. Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
    Validation and test generation for oscillatory noise in VLSI interconnects. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:289-296 [Conf]
  34. I-De Huang, Sandeep K. Gupta, Melvin A. Breuer
    Accurate and Efficient Static Timing Analysis with Crosstalk. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:265-272 [Conf]
  35. Zhiyong Li, John H. Reif, Sandeep K. Gupta
    Synthesizing Efficient Out-of-Core Programs for Block Recursive Algorithms Using Block-Cyclic Data Distributions. [Citation Graph (0, 0)][DBLP]
    ICPP, Vol. 2, 1996, pp:142-149 [Conf]
  36. Sandeep K. Gupta, Wang-Chien Lee, Pradip K. Srimani
    Message from the Chairs. [Citation Graph (0, 0)][DBLP]
    ICPP Workshops, 2000, pp:3- [Conf]
  37. Nabil M. Abdulrazzaq, Sandeep K. Gupta
    Test generation for path-delay faults in one-dimensional iterative logic arrays. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:326-335 [Conf]
  38. Melvin A. Breuer, Sandeep K. Gupta
    Process-Aggravated Noise (PAN): New Validation and Test Problems. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:914-923 [Conf]
  39. Weiyu Chen, Melvin A. Breuer, Sandeep K. Gupta
    Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:809-818 [Conf]
  40. Chih-Ang Chen, Sandeep K. Gupta
    A Methodology to Design Efficient BIST Test Pattern Generators. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:814-823 [Conf]
  41. Weiyu Chen, Sandeep K. Gupta, Melvin A. Breuer
    Test generation in VLSI circuits for crosstalk noise. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:641-0 [Conf]
  42. Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
    Test generation for crosstalk-induced delay in integrated circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:191-200 [Conf]
  43. Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer
    Crosstalk test generation on pseudo industrial circuits: a case study. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:548-557 [Conf]
  44. Hugo Cheung, Sandeep K. Gupta
    A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:386-395 [Conf]
  45. Kun Young Chung, Sandeep K. Gupta
    Structural Delay Testing of Latch-based High-speed Pipelines with Time Borrowing. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1089-1097 [Conf]
  46. Sandeep K. Gupta, Melvin A. Breuer, Jung-Cheun Lien
    Concurrent Control of Multiple BIT Structures. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:431-442 [Conf]
  47. Sandeep K. Gupta, Dhiraj K. Pradhan
    A New Framework for Designing and Analyzing BIST Techniques: Computation of Exact Aliasing Probability. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:329-342 [Conf]
  48. Sandeep K. Gupta, Dhiraj K. Pradhan
    Can Concurrent Checkers Help BIST? [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:140-150 [Conf]
  49. Yuan-Chieh Hsu, Sandeep K. Gupta
    A new path-oriented effect-cause methodology to diagnose delay failures. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:758-0 [Conf]
  50. Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer
    Timing-Independent Testing of Crosstalk in the Presence of Delay Producing Defects Using Surrogate Fault Models. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1024-1033 [Conf]
  51. Zhigang Jiang, Sandeep K. Gupta
    An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:824-833 [Conf]
  52. Mark G. Karpovsky, Sandeep K. Gupta, Dhiraj K. Pradhan
    Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:828-839 [Conf]
  53. Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
    Switch-level delay test of domino logic circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:367-376 [Conf]
  54. Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
    Switch-level delay test. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:171-180 [Conf]
  55. Shahin Nazarian, Hang Huang, Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
    XIDEN: Crosstalk Target Identification Framework. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:365-374 [Conf]
  56. Seongmoon Wang, Sandeep K. Gupta
    LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:85-94 [Conf]
  57. Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer
    Novel Test Pattern Generators for Pseudo-Exhaustive Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:1041-1050 [Conf]
  58. Seongmoon Wang, Sandeep K. Gupta
    ATPG for Heat Dissipation Minimization During Test Application. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:250-258 [Conf]
  59. Seongmoon Wang, Sandeep K. Gupta
    DS-LFSR: A New BIST TPG for Low Heat Dissipation. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:848-857 [Conf]
  60. Melvin A. Breuer, Sandeep K. Gupta
    New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:8- [Conf]
  61. Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
    Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-out. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:358-367 [Conf]
  62. Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
    Test Generation for Maximizing Ground Bounce Considering Circuit Delay. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:151-157 [Conf]
  63. Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
    Analysis of Ground Bounce in Deep Sub-Micron Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:110-116 [Conf]
  64. Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
    Test Generation for Ground Bounce in Internal Logic Circuitry. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:95-105 [Conf]
  65. Nabil M. Abdulrazzaq, Sandeep K. Gupta
    Path-Delay Fault Simulation for Circuits with Large Numbers of Paths for Very Large Test Sets. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:186-196 [Conf]
  66. Sultan M. Al-Harbi, Sandeep K. Gupta
    An Efficient Methodology for Generating Optimal and Uniform March Tests. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:231-239 [Conf]
  67. Sultan M. Al-Harbi, Sandeep K. Gupta
    Generating Complete and Optimal March Tests for Linked Faults in Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:254-266 [Conf]
  68. Sultan M. Al-Harbi, Sandeep K. Gupta
    A Methodology for Transforming Memory Tests for In-System Testing of Direct Mapped Cache Tags. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:394-400 [Conf]
  69. Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
    High Quality Robust Tests for Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:88-93 [Conf]
  70. Hugo Cheung, Sandeep K. Gupta
    A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case Study. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:89-96 [Conf]
  71. Chen-Huan Chiang, Sandeep K. Gupta
    BIST TPGs for Faults in Board Level Interconnect via Boundary Scan. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:376-383 [Conf]
  72. Kun Young Chung, Sandeep K. Gupta
    Low-Cost Scan-Based Delay Testing of Latch-Based Circuits with Time Borrowing. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:8-15 [Conf]
  73. Sandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma
    Delay Fault Testing: How Robust are Our Models? [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:502-503 [Conf]
  74. Shahdad Irajpour, Shahin Nazarian, Lei Wang, Sandeep K. Gupta, Melvin A. Breuer
    Analyzing Crosstalk in the Presence of Weak Bridge Defects. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:385-392 [Conf]
  75. Md. Saffat Quasem, Sandeep K. Gupta
    Designing Reconfigurable Multiple Scan Chains for Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:367-376 [Conf]
  76. Melvin A. Breuer, Sandeep K. Gupta, T. M. Mak
    Defect and Error Tolerance in the Presence of Massive Numbers of Defects. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:216-227 [Journal]
  77. Md. Saffat Quasem, Zhigang Jiang, Sandeep K. Gupta
    Benefits of a SoC-Specific Test Methodology. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:3, pp:68-77 [Journal]
  78. Sandeep K. Gupta, John D. Kececioglu, Alejandro A. Schäffer
    Improving the Practical Space and Time Efficiency of the Shortest-Paths Approach to Sum-of-Pairs Multiple Sequence Alignment. [Citation Graph (0, 0)][DBLP]
    Journal of Computational Biology, 1995, v:2, n:3, pp:459-472 [Journal]
  79. Chih-Ang Chen, Sandeep K. Gupta
    BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:3, pp:257-269 [Journal]
  80. Sandeep K. Gupta, Dhiraj K. Pradhan
    Utilization of On-Line (Concurrent) Checkers During Built-In-Self-Test and Vice Versa. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:1, pp:63-73 [Journal]
  81. Yuan-Chieh Hsu, Sandeep K. Gupta
    A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:11, pp:1312-1318 [Journal]
  82. Mody Lempel, Sandeep K. Gupta
    Zero Aliasing for Modeled Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:11, pp:1283-1295 [Journal]
  83. Dhiraj K. Pradhan, Sandeep K. Gupta
    A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:6, pp:743-763 [Journal]
  84. Dhiraj K. Pradhan, Sandeep K. Gupta, Mark G. Karpovsky
    Aliasing Probability for Multiple Input Signature Analyzer. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:4, pp:586-591 [Journal]
  85. Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer
    Novel Test Pattern Generators for Pseudoexhaustive Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:11, pp:1228-1240 [Journal]
  86. Seongmoon Wang, Sandeep K. Gupta
    ATPG for Heat Dissipation Minimization During Test Application. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:2, pp:256-262 [Journal]
  87. Chih-Ang Chen, Sandeep K. Gupta
    Design of efficient BIST test pattern generators for delay testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1568-1575 [Journal]
  88. Chih-Ang Chen, Sandeep K. Gupta
    Efficient BIST TPG design and test set compaction via input reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:8, pp:692-705 [Journal]
  89. Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
    Analytical models for crosstalk excitation and propagation in VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1117-1131 [Journal]
  90. Mody Lempel, Sandeep K. Gupta, Melvin A. Breuer
    Test embedding with discrete logarithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:554-566 [Journal]
  91. Pankaj Pant, Yuan-Chieh Hsu, Sandeep K. Gupta, Abhijit Chatterjee
    Path delay fault diagnosis in combinational circuits with implicitfault enumeration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1226-1235 [Journal]
  92. Seongmoon Wang, Sandeep K. Gupta
    DS-LFSR: a BIST TPG for low switching activity. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:7, pp:842-851 [Journal]
  93. Seongmoon Wang, Sandeep K. Gupta
    An automatic test pattern generator for minimizing switching activity during scan testing activity. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:8, pp:954-968 [Journal]
  94. Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
    Introducing redundant computations in RTL data paths for reducing BIST resources. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:3, pp:423-445 [Journal]
  95. Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer
    Bounds on pseudoexhaustive test lengths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:420-431 [Journal]

  96. SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement. [Citation Graph (, )][DBLP]


  97. Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules. [Citation Graph (, )][DBLP]


  98. Approximate logic synthesis for error tolerant applications. [Citation Graph (, )][DBLP]


  99. Accurate modeling and fault simulation of Byzantine resistive bridges. [Citation Graph (, )][DBLP]


  100. Characterization of granularity and redundancy for SRAMs for optimal yield-per-area. [Citation Graph (, )][DBLP]


  101. Data Partitioning and Placement Schemes for Matrix Multiplications on a PIM Architecture. [Citation Graph (, )][DBLP]


  102. An Industrial Case Study of Sticky Path-Delay Faults. [Citation Graph (, )][DBLP]


  103. Matrix Inversion on a PIM (Processor-in-Memory). [Citation Graph (, )][DBLP]


Search in 0.029secs, Finished in 0.036secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002