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Title:
Author:
Melvin A. Breuer: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
    A new framework for static timing analysis, incremental timing refinement, and timing simulation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:102-107 [Conf]
  2. Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
    Test generation for crosstalk-induced faults: framework and computational result. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:305-310 [Conf]
  3. Melvin A. Breuer
    Intelligible Test Techniques to Support Error-Tolerance. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:386-393 [Conf]
  4. Melvin A. Breuer, Kwang-Ting Cheng
    Challenges for the Academic Test Community. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:4-0 [Conf]
  5. Melvin A. Breuer, Sandeep K. Gupta, Shahin Nazarian
    Efficient Identification of Crosstalk Induced Slowdown Targets. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:124-131 [Conf]
  6. Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
    An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:174-177 [Conf]
  7. Lei Wang, Sandeep K. Gupta, Melvin A. Breuer
    Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip Interconnects. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:440-447 [Conf]
  8. Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
    A New Gate Delay Model for Simultaneous Switching and Its Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:289-294 [Conf]
  9. Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer
    SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:26-29 [Conf]
  10. Ishwar Parulkar, Melvin A. Breuer, Charles Njinda
    Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:345-356 [Conf]
  11. Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
    Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:395-401 [Conf]
  12. Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
    Lower Bounds on Test Resources for Scheduled Data Flow Graphs. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:143-148 [Conf]
  13. Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
    Introducing Redundant Computations in a Behavior for Reducing BIST Resources. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:548-553 [Conf]
  14. Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer
    An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:242-248 [Conf]
  15. Melvin A. Breuer, Xi-an Zhu
    A knowledge based system for selecting a test methodology for a PLA. [Citation Graph (0, 0)][DBLP]
    DAC, 1985, pp:259-265 [Conf]
  16. Salim U. Chowdhury, Melvin A. Breuer
    The construction of minimal area power and ground nets for VLSI circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1985, pp:794-797 [Conf]
  17. Shahin Nazarian, Massoud Pedram, Sandeep K. Gupta, Melvin A. Breuer
    STAX: statistical crosstalk target set compaction. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:172-177 [Conf]
  18. Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
    Scheduling and Module Assignment for Reducing Bist Resources. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:66-73 [Conf]
  19. Melvin A. Breuer
    Determining error rate in error tolerant VLSI chips. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:321-326 [Conf]
  20. Suriyaprakash Natarajan, Melvin A. Breuer, Sandeep K. Gupta
    Process Variations and their Impact on Circuit Operation. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:73-0 [Conf]
  21. Melvin A. Breuer
    Multi-media Applications and Imprecise Computation. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:2-7 [Conf]
  22. Sen-Pin Lin, Sandeep K. Gupta, Melvin A. Breuer
    A Low Cost BIST Methodology and Associated Novel Test Pattern Generator. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:106-112 [Conf]
  23. Xi-an Zhu, Melvin A. Breuer
    A Knowledge-Based TDM Selection System. [Citation Graph (0, 0)][DBLP]
    FJCC, 1986, pp:854-863 [Conf]
  24. Melvin A. Breuer
    Fault Detection in a Linear Cascade of Identical Machines [Citation Graph (0, 0)][DBLP]
    FOCS, 1968, pp:235-243 [Conf]
  25. Rajesh Gupta, Melvin A. Breuer
    Ordering Storage Elements in a Single Scan Chain. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:408-411 [Conf]
  26. Kuen-Jong Lee, Rajiv Gupta, Melvin A. Breuer
    A New Method for Assigning Signal Flow Directions to MOS Transistors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:492-495 [Conf]
  27. Sen-Pin Lin, Charles Njinda, Melvin A. Breuer
    A Systematic Approach for Designing Testable VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:496-499 [Conf]
  28. Debaditya Mukherjee, Charles Njinda, Melvin A. Breuer
    Synthesis of Optimal 1-Hot Coded On-Chip Controllers for BIST Hardware. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:236-239 [Conf]
  29. Debaditya Mukherjee, Massoud Pedram, Melvin A. Breuer
    Merging multiple FSM controllers for DFT/BIST hardware. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:720-725 [Conf]
  30. Sridhar Narayanan, Melvin A. Breuer
    Reconfigurable scan chains: a novel approach to reduce test application time. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:710-715 [Conf]
  31. Sridhar Narayanan, Rajesh Gupta, Melvin A. Breuer
    Configuring multiple scan chains for minimum test time. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:4-8 [Conf]
  32. Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
    Validation and test generation for oscillatory noise in VLSI interconnects. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:289-296 [Conf]
  33. I-De Huang, Sandeep K. Gupta, Melvin A. Breuer
    Accurate and Efficient Static Timing Analysis with Crosstalk. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:265-272 [Conf]
  34. Rajiv Gupta, Melvin A. Breuer
    An Extensible User Interface for an Object-Oriented VLSI CAD Framework. [Citation Graph (0, 0)][DBLP]
    ICSI, 1990, pp:559-568 [Conf]
  35. Melvin A. Breuer
    Let's Think Analog. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:2-5 [Conf]
  36. Magdy S. Abadir, Melvin A. Breuer
    Scan Path with Look Ahead Shifting (SPLASH). [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:696-704 [Conf]
  37. Melvin A. Breuer, Sandeep K. Gupta
    Process-Aggravated Noise (PAN): New Validation and Test Problems. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:914-923 [Conf]
  38. Melvin A. Breuer, Jung-Cheun Lien
    A Test and Maintenance Controller for a Module Containing Testable Chips. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:502-513 [Conf]
  39. Weiyu Chen, Melvin A. Breuer, Sandeep K. Gupta
    Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:809-818 [Conf]
  40. Weiyu Chen, Sandeep K. Gupta, Melvin A. Breuer
    Test generation in VLSI circuits for crosstalk noise. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:641-0 [Conf]
  41. Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
    Test generation for crosstalk-induced delay in integrated circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:191-200 [Conf]
  42. Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer
    Crosstalk test generation on pseudo industrial circuits: a case study. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:548-557 [Conf]
  43. Sandeep K. Gupta, Melvin A. Breuer, Jung-Cheun Lien
    Concurrent Control of Multiple BIT Structures. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:431-442 [Conf]
  44. Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer
    Timing-Independent Testing of Crosstalk in the Presence of Delay Producing Defects Using Surrogate Fault Models. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1024-1033 [Conf]
  45. Jung-Cheun Lien, Melvin A. Breuer
    Maximal Diagnosis for Wiring Networks. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:96-105 [Conf]
  46. Sridhar Narayanan, Charles Njinda, Melvin A. Breuer
    Optimal Sequencing of Scan Registers. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:293-302 [Conf]
  47. Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
    Switch-level delay test of domino logic circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:367-376 [Conf]
  48. Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
    Switch-level delay test. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:171-180 [Conf]
  49. Shahin Nazarian, Hang Huang, Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
    XIDEN: Crosstalk Target Identification Framework. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:365-374 [Conf]
  50. Debaditya Mukherjee, Massoud Pedram, Melvin A. Breuer
    Control Strategies for Chip-Based DFT/BIST Hardware. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:893-902 [Conf]
  51. Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer
    Novel Test Pattern Generators for Pseudo-Exhaustive Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:1041-1050 [Conf]
  52. Melvin A. Breuer, Sandeep K. Gupta
    New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:8- [Conf]
  53. Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
    Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-out. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:358-367 [Conf]
  54. Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
    Test Generation for Maximizing Ground Bounce Considering Circuit Delay. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:151-157 [Conf]
  55. Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
    Analysis of Ground Bounce in Deep Sub-Micron Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:110-116 [Conf]
  56. Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
    Test Generation for Ground Bounce in Internal Logic Circuitry. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:95-105 [Conf]
  57. Melvin A. Breuer
    High End and Low End Applications for Defective Chips: Enhanced Availability and Acceptability. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:473-474 [Conf]
  58. Melvin A. Breuer, Bozena Kaminska, J. McDermid, V. Rayapathi, Donald L. Wheater
    Will 0.1um Digital Circuits Require Mixed-Signal Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:186-187 [Conf]
  59. Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
    High Quality Robust Tests for Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:88-93 [Conf]
  60. Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
    An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:130-135 [Conf]
  61. Shahdad Irajpour, Shahin Nazarian, Lei Wang, Sandeep K. Gupta, Melvin A. Breuer
    Analyzing Crosstalk in the Presence of Weak Bridge Defects. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:385-392 [Conf]
  62. Sridhar Narayanan, Melvin A. Breuer
    Asynchronous multiple scan chain. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:270-276 [Conf]
  63. Melvin A. Breuer, Haiyang (Henry) Zhu
    Error-Tolerance and Multi-Media. [Citation Graph (0, 0)][DBLP]
    IIH-MSP, 2006, pp:521-524 [Conf]
  64. Melvin A. Breuer
    Techniques for the simulation of computer logic. [Citation Graph (0, 0)][DBLP]
    Commun. ACM, 1964, v:7, n:7, pp:443-446 [Journal]
  65. Melvin A. Breuer
    Generation of optimal code for expressions via factorization. [Citation Graph (0, 0)][DBLP]
    Commun. ACM, 1969, v:12, n:6, pp:333-340 [Journal]
  66. Rajiv Gupta, Wesley H. Cheng, Rajesh Gupta, Ido Hardonag, Melvin A. Breuer
    An Object-Oriented VLSI CAD Framework: A Case Study in Rapid Prototyping. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1989, v:22, n:5, pp:28-37 [Journal]
  67. Melvin A. Breuer, Sandeep K. Gupta, T. M. Mak
    Defect and Error Tolerance in the Presence of Massive Numbers of Defects. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:216-227 [Journal]
  68. Rajiv Gupta, Rajagopalan Srinivasan, Melvin A. Breuer
    Reorganizing Circuits to Aid Testability. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1991, v:8, n:3, pp:49-57 [Journal]
  69. Melvin A. Breuer
    Adaptive Computers [Citation Graph (0, 0)][DBLP]
    Information and Control, 1967, v:11, n:4, pp:402-422 [Journal]
  70. Melvin A. Breuer
    Simplification of the Covering Problem with Application to Boolean Expressions. [Citation Graph (0, 0)][DBLP]
    J. ACM, 1970, v:17, n:1, pp:166-181 [Journal]
  71. Sarangan Krishna Kumar, Melvin A. Breuer
    Probabilistic Aspects of Boolean Switching Functions via a New Transform. [Citation Graph (0, 0)][DBLP]
    J. ACM, 1981, v:28, n:3, pp:502-520 [Journal]
  72. Melvin A. Breuer
    Combinatorial Equivalence of (0, 1) Circulant Matrices. [Citation Graph (0, 0)][DBLP]
    J. Comput. Syst. Sci., 1969, v:3, n:1, pp:8-23 [Journal]
  73. Magdy S. Abadir, Melvin A. Breuer
    Test Schedules for VLSI Circuits Having Built-In Test Hardware. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:4, pp:361-367 [Journal]
  74. Miron Abramovici, Melvin A. Breuer
    On Redundancy and Fault Detection in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:11, pp:864-865 [Journal]
  75. Miron Abramovici, Melvin A. Breuer
    Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:6, pp:451-460 [Journal]
  76. Miron Abramovici, Melvin A. Breuer
    Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect-Cause Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1982, v:31, n:12, pp:1165-1172 [Journal]
  77. Prathima Agrawal, Melvin A. Breuer
    Experiments with a Density Router for PC Cards. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:3, pp:262-267 [Journal]
  78. Melvin A. Breuer, Shih-Jeh Chang, Stephen Y. H. Su
    Identification of Multiple Stuck-Type Faults in Combinational Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1976, v:25, n:1, pp:44-54 [Journal]
  79. Melvin A. Breuer, Arthur D. Friedman
    Functional Level Primitives in Test Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:3, pp:223-235 [Journal]
  80. Melvin A. Breuer, Asad A. Ismaeel
    Roving Emulation as a Fault Detection Mechanism. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:11, pp:933-939 [Journal]
  81. Rajesh Gupta, Rajiv Gupta, Melvin A. Breuer
    The BALLAST Methodology for Structured Partial Scan Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:4, pp:538-544 [Journal]
  82. Israel Koren, Melvin A. Breuer
    On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:1, pp:21-27 [Journal]
  83. A. Majumdar, C. S. Raghavendra, Melvin A. Breuer
    Fault Tolerance in Linear Systolic Arrays Using Time Redundancy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:2, pp:269-276 [Journal]
  84. Sridhar Narayanan, Rajesh Gupta, Melvin A. Breuer
    Optimal Configuring of Multiple Scan Chains. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:9, pp:1121-1131 [Journal]
  85. Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer
    Novel Test Pattern Generators for Pseudoexhaustive Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:11, pp:1228-1240 [Journal]
  86. Zhaoliang Pan, Melvin A. Breuer
    Estimating Error Rate in Defective Logic Using Signature Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:5, pp:650-661 [Journal]
  87. Melvin A. Breuer, Majid Sarrafzadeh, Fabio Somenzi
    Fundamental CAD algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:12, pp:1449-1475 [Journal]
  88. Harold W. Carter, Melvin A. Breuer
    Efficient Single-Layer Routing Along a Line of Points. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:4, pp:259-266 [Journal]
  89. Mandalagiri S. Chandrasekhar, Melvin A. Breuer
    Optimal routing of two rectangular blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:4, pp:413-430 [Journal]
  90. Ting-Hua Chen, Melvin A. Breuer
    Automatic Design for Testability Via Testability Measures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:1, pp:3-11 [Journal]
  91. Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
    Analytical models for crosstalk excitation and propagation in VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1117-1131 [Journal]
  92. Salim U. Chowdhury, Melvin A. Breuer
    Optimum design of IC power/ground nets subject to reliability constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:7, pp:787-796 [Journal]
  93. Kuen-Jong Lee, Melvin A. Breuer
    Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:5, pp:659-670 [Journal]
  94. Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer
    SWiTEST: a switch level test generation system for CMOS combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:625-637 [Journal]
  95. Kuen-Jong Lee, Chih-Nan Wang, Rajiv Gupta, Melvin A. Breuer
    An integrated system for assigning signal flow directions to CMOS transistors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1445-1458 [Journal]
  96. Mody Lempel, Sandeep K. Gupta, Melvin A. Breuer
    Test embedding with discrete logarithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:554-566 [Journal]
  97. Sridhar Narayanan, Melvin A. Breuer
    Reconfiguration techniques for a single scan chain. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:750-765 [Journal]
  98. Sarma Sastry, Melvin A. Breuer
    Detectability of CMOS stuck-open faults using random and pseudorandom test sequences. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:9, pp:933-946 [Journal]
  99. Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
    Introducing redundant computations in RTL data paths for reducing BIST resources. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:3, pp:423-445 [Journal]
  100. Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
    Reduction of detected acceptable faults for yield improvement via error-tolerance. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1599-1604 [Conf]
  101. Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer
    Bounds on pseudoexhaustive test lengths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:420-431 [Journal]

  102. SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement. [Citation Graph (, )][DBLP]


  103. Hardware that produces bounded rather than exact results. [Citation Graph (, )][DBLP]


  104. Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules. [Citation Graph (, )][DBLP]


  105. Basing Acceptable Error-Tolerant Performance on Significance-Based Error-rate (SBER). [Citation Graph (, )][DBLP]


  106. An Illustrated Methodology for Analysis of Error Tolerance. [Citation Graph (, )][DBLP]


  107. Clarifying the record on testability cost functions. [Citation Graph (, )][DBLP]


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