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Zaid Al-Ars: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zaid Al-Ars, A. J. van de Goor
    Impact of memory cell array bridges on the faulty behavior in embedded DRAMs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:282-289 [Conf]
  2. Zaid Al-Ars, A. J. van de Goor
    DRAM Specific Approximation of the Faulty Behavior of Cell Defects. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:98-103 [Conf]
  3. Zaid Al-Ars, A. J. van de Goor
    Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:24-27 [Conf]
  4. Zaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev Richter
    A Memory Specific Notation for Fault Modeling. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:43-0 [Conf]
  5. Zaid Al-Ars, Said Hamdioui, Jörg E. Vollrath
    Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:434-439 [Conf]
  6. Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers
    March SL: A Test For All Static Linked Memory Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:372-377 [Conf]
  7. Said Hamdioui, John D. Reyes, Zaid Al-Ars
    Evaluation of Intra-Word Faults in Word-Oriented RAMs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:283-288 [Conf]
  8. Zaid Al-Ars, A. J. van de Goor
    Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:496-503 [Conf]
  9. Zaid Al-Ars, A. J. van de Goor
    Modeling Techniques and Tests for Partial Faults in Memory Devices. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:89-93 [Conf]
  10. Zaid Al-Ars, A. J. van de Goor
    Soft Faults and the Importance of Stresses in Memory Testing. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1084-1091 [Conf]
  11. Zaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev Richter
    Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10484-10489 [Conf]
  12. Zaid Al-Ars, Said Hamdioui, A. J. van de Goor
    Space of DRAM fault models and corresponding testing. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1252-1257 [Conf]
  13. Zaid Al-Ars, Said Hamdioui, Georg Mueller, A. J. van de Goor
    Framework for Fault Analysis and Test Generation in DRAMs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1020-1021 [Conf]
  14. Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev
    Manifestation of Precharge Faults in High Speed DRAM Devices. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:179-184 [Conf]
  15. Zaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev Richter
    Simulation based analysis of temperature effect on the faulty behavior of embedded DRAMs. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:783-792 [Conf]
  16. Zaid Al-Ars, A. J. van de Goor
    Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests. [Citation Graph (0, 0)][DBLP]
    MTDT, 2001, pp:59-64 [Conf]
  17. Zaid Al-Ars, A. J. van de Goor
    Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:27-32 [Conf]
  18. Zaid Al-Ars, Said Hamdioui, A. J. van de Goor
    A Fault Primitive Based Analysis of Linked Faults in RAMs. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:33-0 [Conf]
  19. Zaid Al-Ars, Martin Herzog, Ivo Schanstra, A. J. van de Goor
    Influence of Bit Line Twisting on the Faulty Behavior of DRAMs. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:32-37 [Conf]
  20. A. J. van de Goor, Said Hamdioui, Zaid Al-Ars
    The Effectiveness of the Scan Test and Its New Variants. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:26-31 [Conf]
  21. Zaid Al-Ars, A. J. van de Goor
    Approximating Infinite Dynamic Behavior for DRAM Cell Defects. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:401-406 [Conf]
  22. Zaid Al-Ars, Said Hamdioui, A. J. van de Goor
    Effects of Bit Line Coupling on the Faulty Behavior of DRAMs. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:117-122 [Conf]
  23. A. J. van de Goor, Zaid Al-Ars
    Functional Memory Faults: A Formal Notation and a Taxonomy. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:281-290 [Conf]
  24. Said Hamdioui, Zaid Al-Ars, A. J. van de Goor
    Testing Static and Dynamic Faults in Random Access Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:395-400 [Conf]
  25. Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev
    Optimizing Test Length for Soft Faults in DRAM Devices. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:59-66 [Conf]
  26. Zaid Al-Ars, A. J. van de Goor
    Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:3, pp:293-309 [Journal]
  27. Said Hamdioui, Zaid Al-Ars, A. J. van de Goor
    Opens and Delay Faults in CMOS RAM Address Decoders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:12, pp:1630-1639 [Journal]
  28. Zaid Al-Ars, A. J. van de Goor
    Test generation and optimization for DRAM cell defects using electrical simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1371-1384 [Journal]
  29. Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers
    Linked faults in random access memories: concept, fault models, test algorithms, and industrial results. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:737-757 [Journal]
  30. Said Hamdioui, Zaid Al-Ars, Javier Jiménez, Jose Calero
    PPM Reduction on Embedded Memories in System on Chip. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:85-90 [Conf]

  31. New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults. [Citation Graph (, )][DBLP]


  32. Fault Diagnosis Using Test Primitives in Random Access Memories. [Citation Graph (, )][DBLP]


  33. Acceleration of Smith-Waterman using Recursive Variable Expansion. [Citation Graph (, )][DBLP]


  34. INDEXYS, a Logical Step beyond GENESYS. [Citation Graph (, )][DBLP]


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