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A. J. van de Goor: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zaid Al-Ars, A. J. van de Goor
    Impact of memory cell array bridges on the faulty behavior in embedded DRAMs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:282-289 [Conf]
  2. Zaid Al-Ars, A. J. van de Goor
    DRAM Specific Approximation of the Faulty Behavior of Cell Defects. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:98-103 [Conf]
  3. Zaid Al-Ars, A. J. van de Goor
    Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:24-27 [Conf]
  4. Zaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev Richter
    A Memory Specific Notation for Fault Modeling. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:43-0 [Conf]
  5. Serge N. Demidenko, A. J. van de Goor, S. Henderson, P. Knoppers
    Simulation and Development of Short Transparent Tests for RAM. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:164-0 [Conf]
  6. A. J. van de Goor
    Answers to the Key Issues. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:520- [Conf]
  7. A. J. van de Goor, G. N. Gaydadjiev
    Realistic Linked Memory Cell Array Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:183-188 [Conf]
  8. A. J. van de Goor, J. E. Simonse
    Defining SRAM Resistive Defects and Their Simulation Stimuli. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:33-40 [Conf]
  9. Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers
    March SL: A Test For All Static Linked Memory Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:372-377 [Conf]
  10. Said Hamdioui, A. J. van de Goor
    An experimental analysis of spot defects in SRAMs: realistic fault models and tests. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:131-138 [Conf]
  11. Said Hamdioui, A. J. van de Goor
    Consequences of Port Restriction on Testing Address Decoders in Two-Port Memories. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:340-347 [Conf]
  12. Said Hamdioui, A. J. van de Goor
    March Tests for Word-Oriented Two-Port Memories. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:53-0 [Conf]
  13. Said Hamdioui, A. J. van de Goor, David Eastwick, Mike Rodgers
    Detecting Unique Faults in Multi-port SRAMs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:37-42 [Conf]
  14. Matthias Klaus, A. J. van de Goor
    Tests for Resistive and Capacitive Defects in Address Decoders. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:31-36 [Conf]
  15. Mario H. Konijnenburg, Hans van der Linden, A. J. van de Goor
    Fault (In)Dependent Cost Estimates and Conflict-Directed Backtracking to Guide Sequential Circuit Test Generation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:185-191 [Conf]
  16. J. Th. van der Linden, M. H. Konijnenburg, A. J. van de Goor
    Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Restrictors. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:29-33 [Conf]
  17. J. Th. van der Linden, M. H. Konijnenburg, A. J. van de Goor
    Complete Search in Test Generation for Industrial Circuits with Improved Bus-Conflict Detection. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:212-0 [Conf]
  18. Zaid Al-Ars, A. J. van de Goor
    Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:496-503 [Conf]
  19. Zaid Al-Ars, A. J. van de Goor
    Modeling Techniques and Tests for Partial Faults in Memory Devices. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:89-93 [Conf]
  20. Zaid Al-Ars, A. J. van de Goor
    Soft Faults and the Importance of Stresses in Memory Testing. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1084-1091 [Conf]
  21. Zaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev Richter
    Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10484-10489 [Conf]
  22. Zaid Al-Ars, Said Hamdioui, A. J. van de Goor
    Space of DRAM fault models and corresponding testing. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1252-1257 [Conf]
  23. Zaid Al-Ars, Said Hamdioui, Georg Mueller, A. J. van de Goor
    Framework for Fault Analysis and Test Generation in DRAMs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1020-1021 [Conf]
  24. A. J. van de Goor, Magdy S. Abadir, Alan Carlin
    Minimal Test for Coupling Faults in Word-Oriented Memories. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:944-948 [Conf]
  25. A. J. van de Goor, J. de Neef
    Industrial Evaluation of DRAM Tests. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:623-630 [Conf]
  26. A. J. van de Goor, Issam B. S. Tlili
    March Tests for Word-Oriented Memories. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:501-0 [Conf]
  27. M. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor
    Illegal State Space Identification for Sequential Circuit Test Generation. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:741-746 [Conf]
  28. Ivo Schanstra, A. J. van de Goor
    Consequences of RAM Bitline Twisting for Test Coverage. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11176-11177 [Conf]
  29. A. J. van de Goor, Ivo Schanstra
    Address and Data Scrambling: Causes and Impact on Memory Tests. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:128-136 [Conf]
  30. A. J. van de Goor, Yervant Zorian, Ivo Schanstra
    Functional Tests for Ring-Address SRAM-type FIFOs. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:666- [Conf]
  31. Gert-Jan Tromp, A. J. van de Goor
    Logic Synthesis of 100-percent Testable Logic Networks. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:428-431 [Conf]
  32. Vlad. Hert, A. J. van de Goor
    Truth Table Verification for one-Dimensional CMOS ILA's. [Citation Graph (0, 0)][DBLP]
    Fault-Tolerant Computing Systems, 1991, pp:205-216 [Conf]
  33. Fabian Klass, Michael J. Flynn, A. J. van de Goor
    A 16x16-bit Static CMOS Wave-Pipelined Multiplier. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:143-146 [Conf]
  34. Zaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev Richter
    Simulation based analysis of temperature effect on the faulty behavior of embedded DRAMs. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:783-792 [Conf]
  35. M. J. Geuzebroek, J. Th. van der Linden, A. J. van de Goor
    Test point insertion for compact test sets. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:292-301 [Conf]
  36. M. J. Geuzebroek, J. Th. van der Linden, A. J. van de Goor
    Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:138-147 [Conf]
  37. A. J. van de Goor, P. C. M. van der Arend, Gert-Jan Tromp
    Locating Bridging Faults in Memory Arrays. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:685-694 [Conf]
  38. A. J. van de Goor, Said Hamdioui, Rob Wadsworth
    Detecting Faults in the Peripheral Circuits and an Evaluation of SRAM Tests. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:114-123 [Conf]
  39. A. J. van de Goor, Mike Lin
    The Implementation of Pseudo-Random Memory Tests on Commercial Memory Testers. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:226-235 [Conf]
  40. A. J. van de Goor, A. Paalvast
    Industrial evaluation of DRAM SIMM tests. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:426-435 [Conf]
  41. A. J. van de Goor, B. Smit
    Generating March Tests Automatically. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:870-878 [Conf]
  42. A. J. van de Goor, Ivo Schanstra
    Industrial evaluation of stress combinations for march tests applied to SRAMs. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:983-992 [Conf]
  43. A. J. van de Goor, Th. J. W. Verhallen
    Functional Testing of Current Microprocessors (applied to the Intel i860TM). [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:684-695 [Conf]
  44. Said Hamdioui, A. J. van de Goor
    Consequences of port restrictions on testing two-port memories. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:63-72 [Conf]
  45. Said Hamdioui, A. J. van de Goor
    Port interference faults in two-port memories. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1001-1010 [Conf]
  46. M. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor
    Test Pattern Generation with Restrictors. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:598-605 [Conf]
  47. M. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor
    Accelerated Compact Test Set Generation for Three-State Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:29-38 [Conf]
  48. M. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor
    Sequential Test Generation with Advanced Illegal State Search. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:733-742 [Conf]
  49. M. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor
    Testability of the Philips 80C51 micro-controller. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:820-829 [Conf]
  50. J. Th. van der Linden, M. H. Konijnenburg, A. J. van de Goor
    Parallel Pattern Fast Fault Simulation for Three-State Circuits and Bidirectional I/O. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:604-613 [Conf]
  51. Jos van Sas, Erik Huyskens, Hans Naert, Fred Schell, A. J. van de Goor
    Coping with Re-usability Using Sequential ATPG: A Practical Case Study. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:252-261 [Conf]
  52. Ivo Schanstra, Dharmajaya Lukita, A. J. van de Goor, Kees Veelenturf, Paul J. van Wijnen
    Semiconductor manufacturing process monitoring using built-in self-test for embedded memories. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:872-0 [Conf]
  53. Yervant Zorian, A. J. van de Goor, Ivo Schanstra
    An Effective BIST Scheme for Ring-Address Type FIFOs. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:378-387 [Conf]
  54. A. J. van de Goor, Henk Corporaal
    DOAS: an object oriented architecture supporting secure languages. [Citation Graph (0, 0)][DBLP]
    MICRO, 1989, pp:127-134 [Conf]
  55. Zaid Al-Ars, A. J. van de Goor
    Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests. [Citation Graph (0, 0)][DBLP]
    MTDT, 2001, pp:59-64 [Conf]
  56. Zaid Al-Ars, A. J. van de Goor
    Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:27-32 [Conf]
  57. Zaid Al-Ars, Said Hamdioui, A. J. van de Goor
    A Fault Primitive Based Analysis of Linked Faults in RAMs. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:33-0 [Conf]
  58. Zaid Al-Ars, Martin Herzog, Ivo Schanstra, A. J. van de Goor
    Influence of Bit Line Twisting on the Faulty Behavior of DRAMs. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:32-37 [Conf]
  59. A. J. van de Goor, Said Hamdioui, Zaid Al-Ars
    The Effectiveness of the Scan Test and Its New Variants. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:26-31 [Conf]
  60. Said Hamdioui, A. J. van de Goor, David Eastwick, Mike Rodgers
    Realistic Fault Models and Test Procedures for Multi-Port SRAMs. [Citation Graph (0, 0)][DBLP]
    MTDT, 2001, pp:65-72 [Conf]
  61. Said Hamdioui, Georgi Gaydadjiev, A. J. van de Goor
    The State-of-Art and Future Trends in Testing Embedded Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:54-59 [Conf]
  62. Said Hamdioui, A. J. van de Goor, Mike Rodgers
    March SS: A Test for All Static Simple RAM Faults. [Citation Graph (0, 0)][DBLP]
    MTDT, 2002, pp:95-100 [Conf]
  63. Said Hamdioui, A. J. van de Goor, Mike Rodgers, David Eastwick
    March Tests for Realistic Faults in Two-Port Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 2000, pp:73-78 [Conf]
  64. Daniel P. Van der Velde, A. J. van de Goor
    Designing a Memory Module Tester. [Citation Graph (0, 0)][DBLP]
    MTDT, 1999, pp:91-0 [Conf]
  65. A. J. van de Goor, A. Moolenaar
    UNIX I/O in a Multiprocessor System. [Citation Graph (0, 0)][DBLP]
    USENIX Winter, 1988, pp:251-258 [Conf]
  66. Zaid Al-Ars, A. J. van de Goor
    Approximating Infinite Dynamic Behavior for DRAM Cell Defects. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:401-406 [Conf]
  67. Zaid Al-Ars, Said Hamdioui, A. J. van de Goor
    Effects of Bit Line Coupling on the Faulty Behavior of DRAMs. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:117-122 [Conf]
  68. A. J. van de Goor, Zaid Al-Ars
    Functional Memory Faults: A Formal Notation and a Taxonomy. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:281-290 [Conf]
  69. A. J. van de Goor, G. N. Gaydadjiev, V. G. Mikitjuk, Vyacheslav N. Yarmolik
    March LR: a test for realistic linked faults. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:272-280 [Conf]
  70. A. J. van de Goor, Said Hamdioui
    Fault Models and Tests for Two-Port Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:401-410 [Conf]
  71. A. J. van de Goor, Issam B. S. Tlili
    Disturb Neighborhood Pattern Sensitive Fault. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:37-47 [Conf]
  72. Said Hamdioui, Zaid Al-Ars, A. J. van de Goor
    Testing Static and Dynamic Faults in Random Access Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:395-400 [Conf]
  73. Said Hamdioui, A. J. van de Goor, Mike Rodgers
    Detecting Intra-Word Faults in Word-Oriented Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:241-247 [Conf]
  74. M. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor
    Compact test sets for industrial circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:358-366 [Conf]
  75. M. D. Janssens, J. K. Annot, A. J. van de Goor
    Adapting UNIX for a Multiprocessor Environment. [Citation Graph (0, 0)][DBLP]
    Commun. ACM, 1986, v:29, n:9, pp:895-901 [Journal]
  76. A. J. van de Goor, C. A. Verruijt
    An Overview of Deterministic Functional RAM Chip Testing. [Citation Graph (0, 0)][DBLP]
    ACM Comput. Surv., 1990, v:22, n:1, pp:5-33 [Journal]
  77. A. J. van de Goor
    An Industrial Evaluation of DRAM Tests. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:5, pp:430-440 [Journal]
  78. A. J. van de Goor
    Using March Tests to Test SRAMs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:1, pp:8-14 [Journal]
  79. J. K. Annot, M. D. Janssens, A. J. van de Goor
    Comments on Morris's Starvation-Free Solution to the Mutual Exclusion Problem. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1986, v:23, n:2, pp:91-97 [Journal]
  80. Zaid Al-Ars, A. J. van de Goor
    Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:3, pp:293-309 [Journal]
  81. A. J. van de Goor, Issam B. S. Tlili
    A Systematic Method for Modifying March Tests for Bit-Oriented Memories into Tests for Word-Oriented Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:10, pp:1320-1331 [Journal]
  82. Said Hamdioui, Zaid Al-Ars, A. J. van de Goor
    Opens and Delay Faults in CMOS RAM Address Decoders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:12, pp:1630-1639 [Journal]
  83. Said Hamdioui, A. J. van de Goor
    Efficient Tests for Realistic Faults in Dual-Port SRAMs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:5, pp:460-473 [Journal]
  84. Petra De Jong, A. J. van de Goor
    Test Pattern Generation for API Faults in RAM. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:11, pp:1426-1428 [Journal]
  85. Zaid Al-Ars, A. J. van de Goor
    Test generation and optimization for DRAM cell defects using electrical simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1371-1384 [Journal]
  86. Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers
    Linked faults in random access memories: concept, fault models, test algorithms, and industrial results. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:737-757 [Journal]
  87. Said Hamdioui, A. J. van de Goor
    Thorough testing of any multiport memory with linear tests. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:217-231 [Journal]

  88. New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults. [Citation Graph (, )][DBLP]


  89. March LA: a test for linked memory faults. [Citation Graph (, )][DBLP]


  90. Memory testing with a RISC microcontroller. [Citation Graph (, )][DBLP]


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