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Shianling Wu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu
    Collaboration between Industry and Academia in Test Research. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:17-0 [Conf]
  2. Najmi T. Jarwala, Paul W. Rutkowski, Shianling Wu, Chi W. Yau
    Lessons Learned from Practical Applications of BIST/B-S Technology. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:251-257 [Conf]
  3. B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, P. Hsu, J. Cho, J. Park, H. Chao, Shianling Wu
    At-Speed Logic BIST for IP Cores. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:860-861 [Conf]
  4. Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo
    At-Speed Logic BIST Architecture for Multi-Clock Designs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:475-478 [Conf]
  5. Sivanarayana Mallela, Shianling Wu
    A Sequential Circuit Test Generation System. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:57-61 [Conf]
  6. Carlos G. Parodi, Vishwani D. Agrawal, Michael L. Bushnell, Shianling Wu
    A non-enumerative path delay fault simulator for sequential circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:934-943 [Conf]
  7. Laung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai
    VirtualScan: A New Compressed Scan Technology for Test Cost Reduction. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:916-925 [Conf]
  8. B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, P. Hsu, J. Cho, J. Park, H. Chao, Shianling Wu
    At-Speed Logic BIST for IP Cores [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  9. Analysis of Resistive Bridging Defects in a Synchronizer. [Citation Graph (, )][DBLP]

  10. Logic BIST Architecture for System-Level Test and Diagnosis. [Citation Graph (, )][DBLP]

  11. On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. [Citation Graph (, )][DBLP]

  12. VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG. [Citation Graph (, )][DBLP]

  13. Turbo1500: Core-Based Design for Test and Diagnosis. [Citation Graph (, )][DBLP]

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