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Said Hamdioui: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zaid Al-Ars, Said Hamdioui, Jörg E. Vollrath
    Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:434-439 [Conf]
  2. Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers
    March SL: A Test For All Static Linked Memory Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:372-377 [Conf]
  3. Said Hamdioui, A. J. van de Goor
    An experimental analysis of spot defects in SRAMs: realistic fault models and tests. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:131-138 [Conf]
  4. Said Hamdioui, A. J. van de Goor
    Consequences of Port Restriction on Testing Address Decoders in Two-Port Memories. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:340-347 [Conf]
  5. Said Hamdioui, A. J. van de Goor
    March Tests for Word-Oriented Two-Port Memories. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:53-0 [Conf]
  6. Said Hamdioui, A. J. van de Goor, David Eastwick, Mike Rodgers
    Detecting Unique Faults in Multi-port SRAMs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:37-42 [Conf]
  7. Said Hamdioui, John D. Reyes, Zaid Al-Ars
    Evaluation of Intra-Word Faults in Word-Oriented RAMs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:283-288 [Conf]
  8. Zaid Al-Ars, Said Hamdioui, A. J. van de Goor
    Space of DRAM fault models and corresponding testing. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1252-1257 [Conf]
  9. Zaid Al-Ars, Said Hamdioui, Georg Mueller, A. J. van de Goor
    Framework for Fault Analysis and Test Generation in DRAMs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1020-1021 [Conf]
  10. Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev
    Manifestation of Precharge Faults in High Speed DRAM Devices. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:179-184 [Conf]
  11. A. J. van de Goor, Said Hamdioui, Rob Wadsworth
    Detecting Faults in the Peripheral Circuits and an Evaluation of SRAM Tests. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:114-123 [Conf]
  12. Said Hamdioui, A. J. van de Goor
    Consequences of port restrictions on testing two-port memories. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:63-72 [Conf]
  13. Said Hamdioui, A. J. van de Goor
    Port interference faults in two-port memories. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1001-1010 [Conf]
  14. Zaid Al-Ars, Said Hamdioui, A. J. van de Goor
    A Fault Primitive Based Analysis of Linked Faults in RAMs. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:33-0 [Conf]
  15. A. J. van de Goor, Said Hamdioui, Zaid Al-Ars
    The Effectiveness of the Scan Test and Its New Variants. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:26-31 [Conf]
  16. Said Hamdioui, A. J. van de Goor, David Eastwick, Mike Rodgers
    Realistic Fault Models and Test Procedures for Multi-Port SRAMs. [Citation Graph (0, 0)][DBLP]
    MTDT, 2001, pp:65-72 [Conf]
  17. Said Hamdioui, Georgi Gaydadjiev, A. J. van de Goor
    The State-of-Art and Future Trends in Testing Embedded Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:54-59 [Conf]
  18. Said Hamdioui, A. J. van de Goor, Mike Rodgers
    March SS: A Test for All Static Simple RAM Faults. [Citation Graph (0, 0)][DBLP]
    MTDT, 2002, pp:95-100 [Conf]
  19. Said Hamdioui, A. J. van de Goor, Mike Rodgers, David Eastwick
    March Tests for Realistic Faults in Two-Port Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 2000, pp:73-78 [Conf]
  20. Zaid Al-Ars, Said Hamdioui, A. J. van de Goor
    Effects of Bit Line Coupling on the Faulty Behavior of DRAMs. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:117-122 [Conf]
  21. A. J. van de Goor, Said Hamdioui
    Fault Models and Tests for Two-Port Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:401-410 [Conf]
  22. Said Hamdioui, Zaid Al-Ars, A. J. van de Goor
    Testing Static and Dynamic Faults in Random Access Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:395-400 [Conf]
  23. Said Hamdioui, A. J. van de Goor, Mike Rodgers
    Detecting Intra-Word Faults in Word-Oriented Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:241-247 [Conf]
  24. Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev
    Optimizing Test Length for Soft Faults in DRAM Devices. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:59-66 [Conf]
  25. Said Hamdioui, Zaid Al-Ars, A. J. van de Goor
    Opens and Delay Faults in CMOS RAM Address Decoders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:12, pp:1630-1639 [Journal]
  26. Said Hamdioui, A. J. van de Goor
    Efficient Tests for Realistic Faults in Dual-Port SRAMs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:5, pp:460-473 [Journal]
  27. Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers
    Linked faults in random access memories: concept, fault models, test algorithms, and industrial results. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:737-757 [Journal]
  28. Said Hamdioui, A. J. van de Goor
    Thorough testing of any multiport memory with linear tests. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:217-231 [Journal]
  29. Said Hamdioui, John Eleazar Q. Delos Reyes
    New data-background sequences and their industrial evaluation for word-oriented random-access memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:6, pp:892-904 [Journal]
  30. Said Hamdioui, Zaid Al-Ars, Javier Jiménez, Jose Calero
    PPM Reduction on Embedded Memories in System on Chip. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:85-90 [Conf]

  31. New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults. [Citation Graph (, )][DBLP]


  32. Testing Embedded Memories in the Nano-Era: Will the Existing Approaches Survive?. [Citation Graph (, )][DBLP]


  33. Fault Diagnosis Using Test Primitives in Random Access Memories. [Citation Graph (, )][DBLP]


  34. NBTI modeling in the framework of temperature variation. [Citation Graph (, )][DBLP]


  35. Memory testing with a RISC microcontroller. [Citation Graph (, )][DBLP]


  36. Using RRNS Codes for Cluster Faults Tolerance in Hybrid Memories. [Citation Graph (, )][DBLP]


  37. Emerging non-CMOS nanoelectronic devices - What are they?. [Citation Graph (, )][DBLP]


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