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Publications of Author

1. Zaid Al-Ars, Said Hamdioui, Jörg E. Vollrath
   Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2005, pp:434-439 [Conf]
   
2. Jörg E. Vollrath, Markus Huebl, Ernst Stahl
   Power Analysis of DRAMs. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 1998, pp:334-339 [Conf]
   
3. Jörg E. Vollrath
   Signal Margin Analysis for Memory Sense Amplifiers . [Citation Graph (0, 0)][DBLP]
   DELTA, 2002, pp:123-127 [Conf]
   
4. Jörg E. Vollrath
   Cell Signal Measurement for High-Density DRAMs. [Citation Graph (0, 0)][DBLP]
   ITC, 1997, pp:209-216 [Conf]
   
5. Jörg E. Vollrath, Randall Rooney
   Pseudo fail bit map generation for RAMs during component test and burn-in in a manufacturing environment. [Citation Graph (0, 0)][DBLP]
   ITC, 2001, pp:768-775 [Conf]
   
6. Jörg E. Vollrath
   Synchronous Dynamic Memory Test Construction: A Field Approach. [Citation Graph (0, 0)][DBLP]
   MTDT, 2000, pp:59-64 [Conf]
   
7. Jörg E. Vollrath
   Output Timing Measurement Using an Idd Method. [Citation Graph (0, 0)][DBLP]
   MTDT, 2003, pp:43-46 [Conf]
   
8. Jörg E. Vollrath
   Tutorial: Characterizing SDRAMS. [Citation Graph (0, 0)][DBLP]
   MTDT, 1999, pp:62-0 [Conf]
   
9. Jörg E. Vollrath, Jürg Schwizer, Marcin Gnat, Ralf Schneider, Bret Johnson
   DDR2 DRAM Output Timing Optimization. [Citation Graph (0, 0)][DBLP]
   MTDT, 2006, pp:49-54 [Conf]
   
10. Jörg E. Vollrath
    Testing and Characterization of SDRAMs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:42-50 [Journal]