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Peter Petrov: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sobeeh Almukhaizim, Peter Petrov, Alex Orailoglu
    Faults in Processor Control Subsystems: Testing Correctness and Performance Faults in the Data Prefetching Unit. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:319-324 [Conf]
  2. Peter Petrov, Alex Orailoglu
    Towards effective embedded processors in codesigns: customizable partitioned caches. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:79-84 [Conf]
  3. Peter Petrov, Alex Orailoglu
    Energy frugal tags in reprogrammable I-caches for application-specific embedded processors. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:181-186 [Conf]
  4. Xiangrong Zhou, Peter Petrov
    Energy-efficient address translation for virtual memory support in low-power and real-time embedded processors. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:33-38 [Conf]
  5. Peter Petrov, Alex Orailoglu
    Speeding Up Control-Dominated Applications through Microarchitectural Customizations in Embedded Processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:512-517 [Conf]
  6. Peter Petrov, Daniel Tracy, Alex Orailoglu
    Energy-effcient physically tagged caches for embedded processors with virtual memory. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:17-22 [Conf]
  7. Xiangrong Zhou, Peter Petrov
    Rapid and low-cost context-switch through embedded processor customization for real-time and control applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:352-357 [Conf]
  8. Peter Petrov, Alex Orailoglu
    Power Efficient Embedded Processor Ip's through Application-Specific Tag Compression in Data Caches. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1065-1071 [Conf]
  9. Peter Petrov, Alex Orailoglu
    Power Efficiency through Application-Specific Instruction Memory Transformations. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10030-10035 [Conf]
  10. Peter Petrov, Alex Orailoglu
    Customizable Embedded Processor Architectures. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:468-475 [Conf]
  11. Peter Petrov, Alex Orailoglu
    Low-power Branch Target Buffer for Application-Specific Embedded Processors. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:158-165 [Conf]
  12. Alokika Dash, Peter Petrov
    Energy-Efficient Cache Coherence for Embedded Multi-Processor Systems through Application-Driven Snoop Filtering. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:79-82 [Conf]
  13. Xiangrong Zhou, Peter Petrov
    Low-power cache organization through selective tag translation for embedded processors with virtual memory support. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:398-403 [Conf]
  14. Peter Petrov, Alex Orailoglu
    Compiler-Based Register Name Adjustment for Low-Power Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:523-528 [Conf]
  15. Peter Petrov, Alex Orailoglu
    Virtual Page Tag Reduction for Low-power TLBs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:371-374 [Conf]
  16. Alex Orailoglu, Peter Petrov
    Low-Power Data Memory Communication for Application-Specific Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:219-224 [Conf]
  17. Peter Petrov, Alex Orailoglu
    Data cache energy minimizations through programmable tag size matching to the applications. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:113-117 [Conf]
  18. Xiangrong Zhou, Peter Petrov
    Arithmetic-based address translation for energy-efficient virtual memory support in low-power, real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:86-91 [Conf]
  19. Peter Petrov, Alex Orailoglu
    Application-Specific Instruction Memory Customizations for Power-Efficient Embedded Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:18-25 [Journal]
  20. Peter Petrov, Alex Orailoglu
    Transforming Binary Code for Low-Power Embedded Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:3, pp:21-33 [Journal]
  21. Peter Petrov, Alex Orailoglu
    Performance and power effectiveness in embedded processors customizable partitioned caches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1309-1318 [Journal]
  22. Peter Petrov, Alex Orailoglu
    Tag compression for low power in dynamically customizable embedded processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1031-1047 [Journal]
  23. Peter Petrov, Alex Orailoglu
    A reprogrammable customization framework for efficient branch resolution in embedded processors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:2, pp:452-468 [Journal]
  24. Boyan Dimitrov, Zohel Khalil, Nikolay Kolev, Peter Petrov
    On the Optimal Total Processing Time Using Checkpoints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1991, v:17, n:5, pp:436-442 [Journal]
  25. Peter Petrov, Alex Orailoglu
    Low-power instruction bus encoding for embedded processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:8, pp:812-826 [Journal]
  26. Rakesh Reddy, Peter Petrov
    Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking systems. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:198-207 [Conf]
  27. Peter Petrov, Alex Orailoglu
    Dynamic Tag Reduction for Low-Power Caches in Embedded Systems with Virtual Memory. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2007, v:35, n:2, pp:157-177 [Journal]

  28. Aggressive snoop reduction for synchronized producer-consumer communication in energy-efficient embedded multi-processors. [Citation Graph (, )][DBLP]

  29. Distributed and low-power synchronization architecture for embedded multiprocessors. [Citation Graph (, )][DBLP]

  30. Latency and bandwidth efficient communication through system customization for embedded multiprocessors. [Citation Graph (, )][DBLP]

  31. Compiler-driven register re-assignment for register file power-density and temperature reduction. [Citation Graph (, )][DBLP]

  32. Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms. [Citation Graph (, )][DBLP]

  33. Context-aware TLB preloading for interference reduction in embedded multi-tasked systems. [Citation Graph (, )][DBLP]

  34. The interval page table: virtual memory support in real-time and memory-constrained embedded systems. [Citation Graph (, )][DBLP]

  35. Low-power inter-core communication through cache partitioning in embedded multiprocessors. [Citation Graph (, )][DBLP]

  36. Dynamic and application-driven I-cache partitioning for low-power embedded multitasking. [Citation Graph (, )][DBLP]

  37. Neural regulator design for parabolic distributed parameter systems with constraints in control. [Citation Graph (, )][DBLP]

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