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Santosh Biswas: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. S. Biswas, P. Srikanth, R. Jha, S. Mukhopadhyay, A. Patra, D. Sarkar
    On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:88-93 [Conf]
  2. Santosh Biswas, Siddhartha Mukhopadhyay, Amit Patra
    A BIST Approach to On-Line Monitoring of Digital VLSI Circuits: A CAD Tool. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:184-189 [Conf]
  3. S. Biswas, S. Mukhopadhyay, P. Patra, D. Sarkar
    Concurrent Testing of Digital Circuits for Advanced Fault Models. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:204-209 [Conf]
  4. Santosh Biswas, Siddhartha Mukhopadhyay, Amit Patra
    Optimization of the Theory of FDD of DES for Alleviation of the State Explosion Problem and Development of CAD Tools for On-line Testing of Digital VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:184-0 [Conf]
  5. Santosh Biswas, Siddhartha Mukhopadhyay, Amit Patra
    A discrete event systems approach to online testing of digital VLSI circuits. [Citation Graph (0, 0)][DBLP]
    SMC (2), 2004, pp:1699-1704 [Conf]
  6. Santosh Biswas, Siddhartha Mukhopadhyay, Amit Patra
    A Formal Approach to On-Line Monitoring of Digital VLSI Circuits: Theory, Design and Implementation. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:5, pp:503-537 [Journal]

  7. Layered Higher Order N-grams for Hardening Payload Based Anomaly Intrusion Detection. [Citation Graph (, )][DBLP]


  8. FPGA based chip emulation system for test development and verification of analog and mixed signal circuits (abstract only). [Citation Graph (, )][DBLP]


  9. Distance Based Fast Hierarchical Clustering Method for Large Datasets. [Citation Graph (, )][DBLP]


  10. An Active Intrusion Detection System for LAN Specific Attacks. [Citation Graph (, )][DBLP]


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