The SCEAS System
| |||||||

## Search the dblp DataBase
Amit Patra:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
## Publications of Author- S. Biswas, P. Srikanth, R. Jha, S. Mukhopadhyay, A. Patra, D. Sarkar
**On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models.**[Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2005, pp:88-93 [Conf] - Santosh Biswas, Siddhartha Mukhopadhyay, Amit Patra
**A BIST Approach to On-Line Monitoring of Digital VLSI Circuits: A CAD Tool.**[Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2004, pp:184-189 [Conf] - Soumya Pandit, Sougata Kar, Chittaranjan A. Mandal, Amit Patra
**High level synthesis of higher order continuous time state variable filters with minimum sensitivity and hardware count.**[Citation Graph (0, 0)][DBLP] DATE, 2006, pp:1203-1204 [Conf] - Abhishek Somani, Partha Pratim Chakrabarti, Amit Patra
**Mixing Global and Local Competition in Genetic Optimization based Design Space Exploration of Analog Circuits.**[Citation Graph (0, 0)][DBLP] DATE, 2005, pp:1064-1069 [Conf] - Sushanta K. Mandal, Arijit De, Amit Patra, Shamik Sural
**A simple wide-band compact model and parameter extraction using particle swarm optimization of on-chip spiral inductors for silicon RFICs.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2005, pp:168-171 [Conf] - Soumya Pandit, Chittaranjan A. Mandal, Amit Patra
**A formal approach for high level synthesis of linear analog systems.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2006, pp:345-348 [Conf] - Santosh Biswas, Siddhartha Mukhopadhyay, Amit Patra
**Optimization of the Theory of FDD of DES for Alleviation of the State Explosion Problem and Development of CAD Tools for On-line Testing of Digital VLSI Circuits.**[Citation Graph (0, 0)][DBLP] IOLTS, 2004, pp:184-0 [Conf] - H. N. Nagaraja, Amit Patra, Debaprasad Kastha
**Generalized analysis of integrated magnetic component based low voltage interleaved DC-DC buck converter for efficiency improvement.**[Citation Graph (0, 0)][DBLP] ISCAS (3), 2005, pp:2485-2489 [Conf] - Santosh Biswas, Siddhartha Mukhopadhyay, Amit Patra
**A discrete event systems approach to online testing of digital VLSI circuits.**[Citation Graph (0, 0)][DBLP] SMC (2), 2004, pp:1699-1704 [Conf] - Abhijit Chatterjee, A. Keshavarzi, Amit Patra, Siddhartha Mukhopadhyay
**Test Methodologies in the Deep Submicron Era -- Analog, Mixed-Signal, and RF.**[Citation Graph (0, 0)][DBLP] VLSI Design, 2005, pp:12-13 [Conf] - Sushanta K. Mandal, Arijit De, Amit Patra, Shamik Sural
**A Wide-Band Lumped Element Compact CAD Model of Si-Based Planar Spiral Inductor for RFIC Design.**[Citation Graph (0, 0)][DBLP] VLSI Design, 2006, pp:619-624 [Conf] - Rajarshi Paul, Amit Patra, Shailendra Baranwal, Kaushik Dash
**Design of Second-Order Sub-Bandgap Mixed-Mode Voltage Reference Circuit for Low Voltage Applications.**[Citation Graph (0, 0)][DBLP] VLSI Design, 2005, pp:307-312 [Conf] - Abhishek Somani, P. P. Chakrabarti, Amit Patra
**A Hierarchical Cost Tree Mutation Approach to Optimization of Analog Circuits.**[Citation Graph (0, 0)][DBLP] VLSI Design, 2005, pp:535-538 [Conf] - Pradipta Patra, Amit Patra, Debaprasad Kastha
**On-chip implementation of a multi-output voltage regulator based on single inductor Buck Converter topology.**[Citation Graph (0, 0)][DBLP] VLSI Design, 2007, pp:935-940 [Conf] - Rajarshi Paul, Faruk Nome, Amit Patra, Barry Culpepper
**Trimming methodologies for compensating process variation errors in second-order bandgap voltage reference circuits.**[Citation Graph (0, 0)][DBLP] Circuits, Signals, and Systems, 2005, pp:44-49 [Conf] - Abhishek Somani, P. P. Chakrabarti, Amit Patra
**A model-based hybrid evolutionary algorithm for fast yield-inclusive design space exploration of analog circuits.**[Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf] - Santosh Biswas, Siddhartha Mukhopadhyay, Amit Patra
**A Formal Approach to On-Line Monitoring of Digital VLSI Circuits: Theory, Design and Implementation.**[Citation Graph (0, 0)][DBLP] J. Electronic Testing, 2005, v:21, n:5, pp:503-537 [Journal] **Design of a Two Dimensional PRSI Image Processor.**[Citation Graph (, )][DBLP]**A novel current controlled tri-state boost converter with superior dynamic performance.**[Citation Graph (, )][DBLP]**An efficient approach to model distortion in weakly nonlinear Gm - C filters.**[Citation Graph (, )][DBLP]**Chaos-Modulated Ramp IC for EMI Reduction in PWM Buck Converters- Design and Analysis of Critical Issues.**[Citation Graph (, )][DBLP]**A New Approach for Estimation of On-Resistance and Current Distribution in Power Array Layouts.**[Citation Graph (, )][DBLP]**Systematic Methodology for High-Level Performance Modeling of Analog Systems.**[Citation Graph (, )][DBLP]
Search in 0.060secs, Finished in 0.061secs | |||||||

| |||||||

| |||||||

System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002 for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002 |