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Publications of Author

1. Wuudiann Ke
   Hybrid Pin Control Using Boundary-Scan And Its Applications. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 1996, pp:44-49 [Conf]
   
2. Wuudiann Ke, Premachandran R. Menon
   Synthesis of Delay-Verifiable Two-Level Circuits. [Citation Graph (0, 0)][DBLP]
   EDAC-ETC-EUROASIC, 1994, pp:297-301 [Conf]
   
3. Wuudiann Ke, Premachandran R. Menon
   Delay-Verifiability of Combinational Circuits Based on Primitive Faults. [Citation Graph (0, 0)][DBLP]
   ICCD, 1994, pp:86-90 [Conf]
   
4. Wuudiann Ke
   Backplane Interconnect Test in a Boundary-Scan Environment. [Citation Graph (0, 0)][DBLP]
   ITC, 1996, pp:717-724 [Conf]
   
5. Wuudiann Ke, Duy Le, Najmi T. Jarwala
   A Secure Data Transmission Scheme for 1149.1 Backplane Test Bus. [Citation Graph (0, 0)][DBLP]
   ITC, 1995, pp:789-796 [Conf]
   
6. Wuudiann Ke, Premachandran R. Menon
   Multifault testability of delay-testable circuits. [Citation Graph (0, 0)][DBLP]
   VTS, 1995, pp:400-409 [Conf]
   
7. Wuudiann Ke, Premachandran R. Menon
   Synthesis of Delay-Verifiable Combinational Circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1995, v:44, n:2, pp:213-222 [Journal]
   
8. Wuudiann Ke, Premachandran R. Menon
   Path-delay-fault testable nonscan sequential circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:576-582 [Journal]
   
9. Wuudiann Ke, Premachandran R. Menon
   Delay-testable implementations of symmetric functions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:772-775 [Journal]