The SCEAS System
Navigation Menu

Search the dblp DataBase


Antonio Rubio: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Josep Altet, Antonio Rubio, Hideo Tamamoto
    Analysis of the Feasibility of Dynamic Thermal Testing in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:149-154 [Conf]
  2. Víctor H. Champac, Antonio Rubio, Joan Figueras
    Analysis of the Floating Gate Defect in CMOS. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:101-108 [Conf]
  3. C. Ferrer, D. Dateo, J. Oliver, Antonio Rubio, M. Rullán
    An Approach to the Development of a IDDQ Testable Cell Library. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:46-54 [Conf]
  4. Johan Lambie, Francesc Moll Echeto, José Luis González, Antonio Rubio
    Asynchronous pulse logic cell for threshold logic and Boolean networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:460-463 [Conf]
  5. Douglas Reed, Jason Doege, Antonio Rubio
    Improving Board and System Test: A Proposal to Integrate Boundary Scan and IDDQ. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:577-585 [Conf]
  6. Josep Altet, Antonio Rubio
    Differential Sensing Strategy for Dynamic Thermal Testing of ICs. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:434-439 [Conf]
  7. Josep Altet, Antonio Rubio, E. Schaub, Stefan Dilhaire, Wilfrid Claeys
    Thermal Testing: Fault Location Strategies. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:189-194 [Conf]
  8. Josep Altet, Antonio Rubio, M. Amine Salhi, J. L. Gálvez, Stefan Dilhaire, Ashish Syal, André Ivanov
    Sensing temperature in CMOS circuits for Thermal Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:179-184 [Conf]
  9. Xavier Aragonès, José Luis González, Francesc Moll, Antonio Rubio
    Noise Generation and Coupling Mechanisms in Deep-Submicron ICs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:27-35 [Journal]
  10. Víctor H. Champac, Antonio Rubio, Joan Figueras
    Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:3, pp:359-369 [Journal]
  11. Miquel Roca, Antonio Rubio
    Current testability analysis of feedback bridging faults in CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:10, pp:1299-1305 [Journal]
  12. Antonio Rubio, Noriyoshi Itazaki, Xiaole Xu, Kozo Kinoshita
    An approach to the analysis and detection of crosstalk faults in digital VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:3, pp:387-395 [Journal]
  13. Javier Ramírez, José C. Segura, Carmen Benítez, Ángel de la Torre, Antonio Rubio
    Efficient voice activity detection algorithms using long-term speech information. [Citation Graph (0, 0)][DBLP]
    Speech Communication, 2004, v:42, n:3-4, pp:271-287 [Journal]
  14. Josep Altet, J. M. Rampnoux, Jean-Christophe Batsale, Stefan Dilhaire, Antonio Rubio, Wilfrid Claeys, Stéphane Grauby
    Applications of temperature phase measurements to IC testing. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:1, pp:95-103 [Journal]
  15. Miguel A. Méndez, José Luis González, Diego Mateo, Antonio Rubio
    An investigation on the relation between digital circuitry characteristics and power supply noise spectrum in mixed-signal CMOS integrated circuits. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2005, v:36, n:1, pp:77-84 [Journal]
  16. Rajesh Galivanche, Rohit Kapur, Antonio Rubio
    Testing in the year 2020. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:960-965 [Conf]
  17. Arindam Calomarde, Diego Mateo, Antonio Rubio
    High level spectral-based analysis of power consumption in DSPs systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  18. Arindam Calomarde, Antonio Rubio, Jordi Saludes
    Selective Clock-Gating for Low-Power Synchronous Counters. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:3, pp:217-225 [Journal]

  19. Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability. [Citation Graph (, )][DBLP]

  20. MODEST: a model for energy estimation under spatio-temporal variability. [Citation Graph (, )][DBLP]

  21. Data Dependence of Delay Distribution for a Planar Bus. [Citation Graph (, )][DBLP]

Search in 0.004secs, Finished in 0.005secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002