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Ching-Hwa Cheng: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang
    Charge sharing fault analysis and testing for CMOS domino logic circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:435-440 [Conf]
  2. Yin-He Su, Ching-Hwa Cheng, Shih-Chieh Chang
    Novel techniques for improving testability analysis. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:392-397 [Conf]
  3. Ching-Hwa Cheng
    Adaptable Voltage Scan Testing of Charge-Sharing Faults for Domino Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:147-158 [Conf]
  4. Ching-Hwa Cheng
    Design Scan Test Strategy for Single Phase Dynamic Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:199-0 [Conf]
  5. Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone
    Charge Sharing Fault Detection for CMOS Domino Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:77-85 [Conf]
  6. Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone
    Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:329-337 [Conf]
  7. Yung-Yuan Chen, Ching-Hwa Cheng, Yung-Ci Chou
    An Effective Reconfiguration Process for Fault-Tolerant VLSI/WSI Array Processors. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:421-438 [Conf]
  8. Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang
    Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:387-390 [Conf]
  9. Yung-Yuan Chen, Ching-Hwa Cheng, Jwu-E Chen
    An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:349-354 [Conf]
  10. Hsiang-Hui Huang, Ching-Hwa Cheng
    Using Clock-Vdd to Test and Diagnose the Power-Switch in Power-Gating Circuit. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:110-118 [Conf]
  11. Yung-Yuan Chen, Shambhu J. Upadhyaya, Ching-Hwa Cheng
    A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:12, pp:1363-1371 [Journal]
  12. Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang
    Charge-sharing alleviation and detection for CMOS domino circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:266-280 [Journal]
  13. Chang-Tzu Lin, Tai-Wei Kung, De-Sheng Chen, Yi-Wen Wang, Ching-Hwa Cheng
    Noise-Aware Floorplanning for Fast Power Supply Network Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2028-2031 [Conf]

  14. CKVdd: a self-stabilization ramp-vdd technique for dynamic power reduction. [Citation Graph (, )][DBLP]

  15. A full-synthesizable high-precision built-in delay time measurement circuit. [Citation Graph (, )][DBLP]

  16. Functional Built-In Delay Binning and Calibration Mechanism for On-Chip at-Speed Self Test. [Citation Graph (, )][DBLP]

  17. An All-Digital High-Precision Built-In Delay Time Measurement Circuit. [Citation Graph (, )][DBLP]

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