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Chen-Huan Chiang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chen-Huan Chiang, Sandeep K. Gupta
    BIST TPG for SRAM cluster interconnect testing at board level. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:58-65 [Conf]
  2. Chen-Huan Chiang, Sandeep K. Gupta
    BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:244-252 [Conf]
  3. Chen-Huan Chiang, Sandeep K. Gupta
    Random pattern testable logic synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:125-128 [Conf]
  4. Chen-Huan Chiang, Sandeep K. Gupta
    BIST TPG for faults in system backplanes. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:406-413 [Conf]
  5. Robert W. Barr, Chen-Huan Chiang, Edward L. Wallace
    End-to-end testing for boards and systems using boundary scan. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:585-592 [Conf]
  6. Tapan J. Chakraborty, Chen-Huan Chiang
    A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan Architectur. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:923-929 [Conf]
  7. Chen-Huan Chiang, Paul J. Wheatley, Kenneth Y. Ho, Ken L. Cheung
    Testing and Remote Field Update of Distributed Base Stations in a Wireless Network. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:711-718 [Conf]
  8. Chen-Huan Chiang, Sandeep K. Gupta
    BIST TPGs for Faults in Board Level Interconnect via Boundary Scan. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:376-383 [Conf]
  9. Brendan Mullane, Chen-Huan Chiang, Michael Higgins, Ciaran MacNamee, Tapan J. Chakraborty, Thomas B. Cook
    FPGA Prototyping of a Scan Based System-On-Chip Design. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:121-126 [Conf]

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