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Publications of Author

1. Davide Appello, Fulvio Corno, M. Giovinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
   A P1500 Compliant BIST-Based Approach to Embedded RAM Diagnosis. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2001, pp:97-102 [Conf]
   
2. Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda
   A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques. [Citation Graph (0, 0)][DBLP]
   IOLTW, 2002, pp:206-210 [Conf]
   
3. Davide Appello
   The Yield of Test Outsourcing. [Citation Graph (0, 0)][DBLP]
   ITC, 2002, pp:1215- [Conf]
   
4. Davide Appello, Paolo Bernardi, Alessandra Fudoli, Maurizio Rebaudengo, Matteo Sonza Reorda, Vincenzo Tancorre, Massimo Violante
   Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores. [Citation Graph (0, 0)][DBLP]
   ITC, 2003, pp:379-385 [Conf]
   
5. Aubin Roy, Stephen K. Sunter, Alessandra Fudoli, Davide Appello
   High Accuracy Stimulus Generation for A/D Converter BIST. [Citation Graph (0, 0)][DBLP]
   ITC, 2002, pp:1031-1039 [Conf]
   
6. Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda
   A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques. [Citation Graph (0, 0)][DBLP]
   MTDT, 2002, pp:12-16 [Conf]
   
7. Davide Appello
   Session Abstract. [Citation Graph (0, 0)][DBLP]
   VTS, 2006, pp:240-241 [Conf]
   
8. Davide Appello, Alessandra Fudoli, Katia Giarda, Emil Gizdarski, Ben Mathew, Vincenzo Tancorre
   Yield Analysis of Logic Circuits. [Citation Graph (0, 0)][DBLP]
   VTS, 2004, pp:103-108 [Conf]
   
9. Davide Appello, Vincenzo Tancorre, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda
   On the Automation of the Test Flow of Complex SoCs. [Citation Graph (0, 0)][DBLP]
   VTS, 2006, pp:166-171 [Conf]
   
10. Davide Appello, Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda
    System-in-Package Testing: Problems and Solutions. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:3, pp:203-211 [Journal]
    
11. Davide Appello, Alessandra Fudoli, Katia Giarda, Vincenzo Tancorre, Emil Gizdarski, Ben Mathew
    Understanding Yield Losses in Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:208-215 [Journal]
    
12. 
    Adapting to adaptive testing. [Citation Graph (, )][DBLP]
    
    
13. 
    An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains. [Citation Graph (, )][DBLP]
    
    
14. 
    An I-IP based approach for the monitoring of NBTI effects in SoCs. [Citation Graph (, )][DBLP]
    
    
15. 
    Evaluating Alpha-induced soft errors in embedded microprocessors. [Citation Graph (, )][DBLP]
    
    
16. 
    Automatic Functional Stress Pattern Generation for SoC Reliability Characterization. [Citation Graph (, )][DBLP]