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Matteo Sonza Reorda: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Davide Appello, Fulvio Corno, M. Giovinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    A P1500 Compliant BIST-Based Approach to Embedded RAM Diagnosis. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:97-102 [Conf]
  2. Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    Guaranteeing Testability in Re-encoding for Low Power. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:30-35 [Conf]
  3. Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    FPGA-Based Fault Injection for Microprocessor Systems. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:304-0 [Conf]
  4. Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero
    Effective Techniques for High-Level ATPG. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:225-0 [Conf]
  5. Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero
    Evolutionary Test Program Induction for Microprocessor Design Verification. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:368-373 [Conf]
  6. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero
    A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:56-61 [Conf]
  7. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:68-73 [Conf]
  8. Paolo Camurati, M. Gilli, Paolo Prinetto, Matteo Sonza Reorda
    The Use of Model Checking in ATPG for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:86-95 [Conf]
  9. Mario Baldi, Fulvio Corno, Maurizio Rebaudengo, Paolo Prinetto, Matteo Sonza Reorda, Giovanni Squillero
    Simulation-based verification of network protocols performance. [Citation Graph (0, 0)][DBLP]
    CHARME, 1997, pp:236-251 [Conf]
  10. Marcello Lajolo, Luciano Lavagno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Automatic test bench generation for simulation-based validation. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:136-140 [Conf]
  11. Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Silvano Gai, Paolo Prinetto, Matteo Sonza Reorda
    A New Model for Improving symbolic Product Machine Traversal. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:614-619 [Conf]
  12. Paolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda
    Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:228-233 [Conf]
  13. M. Bellato, Paolo Bernardi, D. Bortolato, A. Candelori, M. Ceschia, A. Paccagnella, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, P. Zambolin
    Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:584-589 [Conf]
  14. Paolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda
    Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:228-233 [Conf]
  15. Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10720-10725 [Conf]
  16. Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda
    An effective technique for minimizing the cost of processor software-based diagnosis in SoCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:412-417 [Conf]
  17. Luis Berrojo, I. Gónzólez, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López
    New Techniques for Speeding-Up Fault-Injection Campaigns. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:847-853 [Conf]
  18. Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero
    Fully Automatic Test Program Generation for Microprocessor Cores. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11006-11011 [Conf]
  19. Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante
    Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:670-0 [Conf]
  20. Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
    Approximate Equivalence Verification of Sequential Circuits via Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:754-755 [Conf]
  21. Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Alberto Manzone, Alessandro Pincetti
    Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:385-389 [Conf]
  22. Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante
    On the test of microprocessor IP cores. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:209-213 [Conf]
  23. Ph. Cheynet, B. Nicolescu, Raoul Velazco, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    System safety through automatic high-level code transformations: an experimental evaluation. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:297-301 [Conf]
  24. O. Goloubeva, Matteo Sonza Reorda, Massimo Violante
    Automatic Generation of Validation Stimuli for Application-Specific Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:188-193 [Conf]
  25. Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Carro, Matteo Sonza Reorda
    On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1290-1295 [Conf]
  26. Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno
    Evaluating System Dependability in a Co-Design Framework. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:586-590 [Conf]
  27. Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10602-10607 [Conf]
  28. Elizabeth M. Rudnick, Roberto Vietti, Akilah Ellis, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:570-576 [Conf]
  29. Paolo Bernardi, Leticia Maria Veiras Bolzani, Matteo Sonza Reorda
    Extended Fault Detection Techniques for Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:55-60 [Conf]
  30. Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits . [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:250-258 [Conf]
  31. Fulvio Corno, Matteo Sonza Reorda, Maurizio Rebaudengo, Massimo Violante
    Optimal Vector Selection for Low Power BIST. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:219-226 [Conf]
  32. Abdelaziz Ammari, Régis Leveugle, Matteo Sonza Reorda, Massimo Violante
    Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:336-343 [Conf]
  33. Lorena Anghel, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero, Raoul Velazco
    Coupling Different Methodologies to Validate Obsolete Microprocessors. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:250-255 [Conf]
  34. Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Jaan Raik, Raimund Ubar
    Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:212-217 [Conf]
  35. Alfredo Benso, Maurizio Rebaudengo, Matteo Sonza Reorda, Pierluigi Civera
    An Integrated HW and SW Fault Injection Environment for Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:117-0 [Conf]
  36. Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:445-453 [Conf]
  37. Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda
    Exploiting an I-IP for In-Field SOC Test. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:404-412 [Conf]
  38. Silvia Chiusano, Fulvio Corno, Matteo Sonza Reorda, Roberto Vietti
    A System for Evaluating On-Line Testability at the RT-level. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:284-291 [Conf]
  39. O. Goloubeva, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Soft-Error Detection Using Control Flow Assertions. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:581-588 [Conf]
  40. J. Pérez, Matteo Sonza Reorda, Massimo Violante
    Dependability Analysis of CAN Networks: An Emulation-Based Approach. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:537-0 [Conf]
  41. Maurizio Rebaudengo, Matteo Sonza Reorda, Marco Torchiano, Massimo Violante
    An Experimental Evaluation of the Effectiveness of Automatic Rule-Based Transformations for Safety-Critical Applications. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:257-265 [Conf]
  42. Maurizio Rebaudengo, Matteo Sonza Reorda, Marco Torchiano, Massimo Violante
    Soft-Error Detection through Software Fault-Tolerance Techniques. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:210-218 [Conf]
  43. Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    A New Functional Fault Model for FPGA Application-Oriented Testing. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:372-380 [Conf]
  44. Matteo Sonza Reorda, Massimo Violante
    Fault List Compaction through Static Timing Analysis for Efficient Fault Injection Experiments. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:263-274 [Conf]
  45. Matteo Sonza Reorda, Massimo Violante
    On-Line Analysis and Perturbation of CAN Networks. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:424-432 [Conf]
  46. Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero
    On the Transformation of Manufacturing Test Sets into On-Line Test Sets for Microprocessors. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:494-504 [Conf]
  47. Carlos Arthur Lang Lisbôa, Luigi Carro, Matteo Sonza Reorda, Massimo Violante
    Online hardening of programs against SEUs and SETs. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:280-290 [Conf]
  48. Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante
    On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core. [Citation Graph (0, 0)][DBLP]
    DSN, 2005, pp:50-58 [Conf]
  49. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Maurizio Damiani, Leonardo Impagliazzo, G. Sartore
    On-line Testing of an Off-the-shelf Microprocessor Board for Safety-critical Applications. [Citation Graph (0, 0)][DBLP]
    EDCC, 1996, pp:190-202 [Conf]
  50. Silvano Gai, Pier Luca Montessoro, Matteo Sonza Reorda
    TORSIM: An Efficient Fault Simulator for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:46-50 [Conf]
  51. Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero
    ARPIA: A High-Level Evolutionary Test Signal Generator. [Citation Graph (0, 0)][DBLP]
    EvoWorkshops, 2001, pp:298-306 [Conf]
  52. Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Prediction of Power Requirements for High-Speed Circuits. [Citation Graph (0, 0)][DBLP]
    EvoWorkshops, 2000, pp:247-254 [Conf]
  53. Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Test Pattern Generation Under Low Power Constraints. [Citation Graph (0, 0)][DBLP]
    EvoWorkshops, 1999, pp:162-170 [Conf]
  54. Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
    Automatic Validation of Protocol Interfaces Described in VHDL. [Citation Graph (0, 0)][DBLP]
    EvoWorkshops, 2000, pp:205-213 [Conf]
  55. Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
    Evolutionary Techniques for Minimizing Test Signals Application Time. [Citation Graph (0, 0)][DBLP]
    EvoWorkshops, 2002, pp:183-189 [Conf]
  56. Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
    Approximate Equivalence Verification for Protocol Interface Implementation via Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    EvoWorkshops, 1999, pp:182-192 [Conf]
  57. Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero
    Automatic Completion and Refinement of Verification Sets for Microprocessor Cores. [Citation Graph (0, 0)][DBLP]
    EvoWorkshops, 2005, pp:205-214 [Conf]
  58. Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:493-502 [Conf]
  59. Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:607-615 [Conf]
  60. Matteo Sonza Reorda, Massimo Violante
    Emulation-Based Analysis of Soft Errors in Deep Sub-micron Circuits. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:616-626 [Conf]
  61. Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero, Luca Sterpone, Massimo Violante
    New evolutionary techniques for test-program generation for complex microprocessor cores. [Citation Graph (0, 0)][DBLP]
    GECCO, 2005, pp:2193-2194 [Conf]
  62. Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    ALPS: A Peak Power Estimation Tool for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:350-353 [Conf]
  63. Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda
    Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:411-416 [Conf]
  64. F. Bianchi, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Roberto Ansaloni
    Boolean Function Manipulation on a Parallel System Using BDDs. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1997, pp:916-928 [Conf]
  65. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    A Parallel Genetic Algorithm for Automatic Generation of Test Sequences for Digital Circuits. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1996, pp:454-459 [Conf]
  66. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva
    A PVM tool for automatic test generation on parallel and distributed systems. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1995, pp:39-44 [Conf]
  67. P. P. Delsanto, S. Biancotto, M. Scalerandi, Maurizio Rebaudengo, Matteo Sonza Reorda
    Exploiting massively parallel architectures for the solution of diffusion and propagation problems. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1995, pp:1-6 [Conf]
  68. Gavril Godza, Maurizio Rebaudengo, Matteo Sonza Reorda
    Using Parallel Genetic Algorithms for Solving the Min-Cut Problem. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1996, pp:985-986 [Conf]
  69. Maurizio Rebaudengo, Matteo Sonza Reorda
    A Cellular Genetic Algorithm for the Floorplan Area Optimization Problem on a SIMD Architecture. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1996, pp:987-988 [Conf]
  70. Gianpiero Cabodi, Silvano Gai, Matteo Sonza Reorda
    Fast Differential Fault Simulation by Dynamic Fault Ordering. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:60-63 [Conf]
  71. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero
    A new Approach for Initialization Sequences Computation for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:381-386 [Conf]
  72. Matteo Sonza Reorda, Maurizio Rebaudengo
    A Genetic Algorithm for Floorplan Area Optimization. [Citation Graph (0, 0)][DBLP]
    International Conference on Evolutionary Computation, 1994, pp:93-96 [Conf]
  73. Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
    Evolving Cellular Automata for Self-Testing Hardware. [Citation Graph (0, 0)][DBLP]
    ICES, 2000, pp:31-40 [Conf]
  74. S. Chuisano, Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    Exploiting Symbolic Techniques within Genetic Algorithms for Power Optimization. [Citation Graph (0, 0)][DBLP]
    ICTAI, 1997, pp:133-0 [Conf]
  75. Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    A Genetic Algorithm for Automatic Generation of Test Logic for Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ICTAI, 1996, pp:10-16 [Conf]
  76. Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante
    A genetic algorithm-based system for generating test programs for microprocessor IP cores. [Citation Graph (0, 0)][DBLP]
    ICTAI, 2000, pp:195-198 [Conf]
  77. Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva
    GATTO: An Intelligent Tool for Automatic Test Pattern Generation for Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ICTAI, 1994, pp:411-417 [Conf]
  78. Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
    Exploiting the Selfish Gene Algorithm for Evolving Cellular Automata. [Citation Graph (0, 0)][DBLP]
    IJCNN (6), 2000, pp:577-584 [Conf]
  79. Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda
    A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:206-210 [Conf]
  80. Paolo Bernardi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante
    On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:115-120 [Conf]
  81. Luis Berrojo, Isabel González, Luis Entrena, Celia López, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
    Analysis of the Equivalences and Dominances of Transient Faults at the RT Level. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:193- [Conf]
  82. Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante
    Hybrid Soft Error Detection by Means of Infrastructure IP Cores. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:79-88 [Conf]
  83. O. Goloubeva, Matteo Sonza Reorda, Massimo Violante
    An RT-level Concurrent Error Detection Technique for Data Dominated Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:159- [Conf]
  84. Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Exploiting FPGA for Accelerating Fault Injection Experiments. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:9-13 [Conf]
  85. B. Nicolescu, Raoul Velazco, Matteo Sonza Reorda
    Effectiveness and Limitations of Various Software Techniques for "Soft Error" Detection: A Comparative Study. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:172-177 [Conf]
  86. B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    New Techniques for Accelerating Fault Injection in VHDL Descriptions. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2000, pp:61-66 [Conf]
  87. Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Analysis of SEU Effects in a Pipelined Processor. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:112-116 [Conf]
  88. Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Ph. Cheynet, B. Nicolescu, Raoul Velazco
    Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2000, pp:17-0 [Conf]
  89. Matteo Sonza Reorda, Massimo Violante
    Accurate and Efficient Analysis of Single Event Transients in VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:101-105 [Conf]
  90. Matteo Sonza Reorda, Luca Sterpone, Massimo Violante
    Efficient Estimation of SEU Effects in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:54-59 [Conf]
  91. Alberto Manzone, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Ernesto Sánchez, Matteo Sonza Reorda
    Integrating BIST Techniques for On-Line SoC Testing. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:235-240 [Conf]
  92. Fabian Vargas, Diogo B. Brum, Dárcio Prestes, Leticia Maria Veiras Bolzani, E. Rhod, Matteo Sonza Reorda
    Introducing SW-Based Fault Handling Mechanisms to Cope with EMI in Embedded Electronics: Are They A Good Remedy? [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:163- [Conf]
  93. Massimo Violante, M. Ceschia, Matteo Sonza Reorda, A. Paccagnella, Paolo Bernardi, Maurizio Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori
    Analyzing SEU Effects in SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:119-123 [Conf]
  94. Matteo Sonza Reorda, Massimo Violante
    Hardware-in-the-Loop-Based Dependability Analysis of Automotive Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:229-234 [Conf]
  95. Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero
    Automatic Test Program Generation from RT-Level Microprocessor Descriptions. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:120-0 [Conf]
  96. Davide Appello, Paolo Bernardi, Alessandra Fudoli, Maurizio Rebaudengo, Matteo Sonza Reorda, Vincenzo Tancorre, Massimo Violante
    Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:379-385 [Conf]
  97. Stefano Barbagallo, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    Testing a Switching Memory in a Telcommunication System. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:947-956 [Conf]
  98. Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    A fault injection environment for microprocessor-based boards. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:768-773 [Conf]
  99. Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    Sequential Circuit Diagnosis Based on Formal Verification Techniques. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:187-196 [Conf]
  100. Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    Making the Circular Self-Test Path Technique Effective for Real Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:949-957 [Conf]
  101. Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    Testability Analysis and ATPG on Behavioral RT-Level VHDL. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:753-759 [Conf]
  102. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    Comparing Topological, Symbolic and GA-based ATPGs: An Experimental Approach. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:39-47 [Conf]
  103. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    Partial Scan Flip Flop Selection for Simulation-Based Sequential ATPGs. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:558-564 [Conf]
  104. Fulvio Corno, Matteo Sonza Reorda, S. Tosato, F. Esposito
    Evaluating the Effects of Transient Faults on Vehicle Dynamic Performance in Automotive Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1332-1339 [Conf]
  105. Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:240-249 [Conf]
  106. Matteo Sonza Reorda
    High-level ATPG: a real topic or an academic amusement? [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1118- [Conf]
  107. Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda
    A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques. [Citation Graph (0, 0)][DBLP]
    MTDT, 2002, pp:12-16 [Conf]
  108. Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda
    Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores. [Citation Graph (0, 0)][DBLP]
    MTV, 2005, pp:55-62 [Conf]
  109. Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda
    Using Infrastructure IPs to Support SW-Based Self-Test of Processor Cores. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:22-27 [Conf]
  110. Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero
    Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets. [Citation Graph (0, 0)][DBLP]
    MTV, 2005, pp:37-41 [Conf]
  111. Paolo Bernardi, Leticia Maria Veiras Bolzani, Alberto Manzone, Marcella Guagliumi Massimo Osella, Massimo Violante, Matteo Sonza Reorda
    Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:3-8 [Conf]
  112. W. Lindsay, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero
    Automatic Test Programs Generation Driven by Internal Performance Counters. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:8-13 [Conf]
  113. Marcello Lajolo, Luciano Lavagno, Matteo Sonza Reorda, Massimo Violante
    Early Power Estimation for System-on-Chip Designs. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:108-117 [Conf]
  114. Silvano Gai, Maurizio Rebaudengo, Matteo Sonza Reorda
    An improved data parallel algorithm for Boolean function manipulation using BDDs. [Citation Graph (0, 0)][DBLP]
    PDP, 1995, pp:33-41 [Conf]
  115. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    Exploiting Competing Subpopulations for Automatic Generation of Test Sequences for Digital Cicuits. [Citation Graph (0, 0)][DBLP]
    PPSN, 1996, pp:792-800 [Conf]
  116. Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero
    Automatic Test Program Generation for Pipeline Processors. [Citation Graph (0, 0)][DBLP]
    SAC, 2003, pp:736-740 [Conf]
  117. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    SAARA: a simulated annealing algorithm for test pattern generation for digital circuits. [Citation Graph (0, 0)][DBLP]
    SAC, 1997, pp:228-232 [Conf]
  118. Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
    Evolving effective CA/CSTP: BIST architectures for sequential circuits. [Citation Graph (0, 0)][DBLP]
    SAC, 2001, pp:345-350 [Conf]
  119. Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
    An evolutionary algorithm for reducing integrated-circuit test application time. [Citation Graph (0, 0)][DBLP]
    SAC, 2002, pp:608-612 [Conf]
  120. Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
    The selfish gene algorithm: a new evolutionary optimization strategy. [Citation Graph (0, 0)][DBLP]
    SAC, 1998, pp:349-355 [Conf]
  121. Alfredo Benso, Maurizio Rebaudengo, Matteo Sonza Reorda
    FlexFi: A Flexible Fault Injection Environment for Microprocessor-Based Systems. [Citation Graph (0, 0)][DBLP]
    SAFECOMP, 1999, pp:323-335 [Conf]
  122. B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Speeding-Up Fault Injection Campaigns in VHDL Models. [Citation Graph (0, 0)][DBLP]
    SAFECOMP, 2000, pp:27-36 [Conf]
  123. Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante
    Automatic generation of test sets for SBST of microprocessor IP cores. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:74-79 [Conf]
  124. Fulvio Corno, Julio Pérez Acle, Matteo Sonza Reorda, Massimo Violante
    A multi-level approach to the dependability analysis of networked systems based on the CAN protocol. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:71-75 [Conf]
  125. J. Pérez, Matteo Sonza Reorda, Massimo Violante
    Accurate Dependability Analysis of CAN-Based Networked Systems. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:337-342 [Conf]
  126. Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Marco Torchiano
    A Source-to-Source Compiler for Generating Dependable Software. [Citation Graph (0, 0)][DBLP]
    SCAM, 2001, pp:35-44 [Conf]
  127. Marcello Lajolo, Matteo Sonza Reorda, Massimo Violante
    Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:371-0 [Conf]
  128. Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda
    A Pattern Ordering Algorithm for Reducing the Size of Fault Dictionaries. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:386-391 [Conf]
  129. Luis Berrojo, Isabel González, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López
    An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:229-236 [Conf]
  130. Stefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    Scan insertion criteria for low design impact. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:26-31 [Conf]
  131. Davide Appello, Vincenzo Tancorre, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda
    On the Automation of the Test Flow of Complex SoCs. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:166-171 [Conf]
  132. Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    Cellular automata for deterministic sequential test pattern generation. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:60-67 [Conf]
  133. Fulvio Corno, Nicola Gaudenzi, Paolo Prinetto, Matteo Sonza Reorda
    On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:424-429 [Conf]
  134. Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Uwe Gläser, Heinrich Theodor Vierhaus
    Improving topological ATPG with symbolic techniques. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:338-343 [Conf]
  135. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    A Test Pattern Generation Methodology for Low-Power Consumption. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:453-459 [Conf]
  136. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva
    A portable ATPG tool for parallel and distributed systems. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:29-34 [Conf]
  137. Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante
    Low Power BIST via Non-Linear Hybrid Cellular Automata. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:29-34 [Conf]
  138. Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
    High-Level Observability for Effective High-Level ATPG. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:411-416 [Conf]
  139. Maurizio Rebaudengo, Matteo Sonza Reorda
    Evaluating the Fault Tolerance Capabilities of Embedded Systems via BDM . [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:452-459 [Conf]
  140. Julio Pérez Acle, Matteo Sonza Reorda, Massimo Violante
    Early, Accurate Dependability Analysis of CAN-Based Networked Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:1, pp:38-45 [Journal]
  141. Davide Appello, Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda
    System-in-Package Testing: Problems and Solutions. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:3, pp:203-211 [Journal]
  142. Stefano Barbagallo, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    Integrating Online and Offline Testing of a Switching Memory. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:1, pp:63-70 [Journal]
  143. Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda, Stefano Barbagallo, Andrea Burri, Davide Medina
    Industrial BIST of Embedded RAMs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:3, pp:86-95 [Journal]
  144. Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    Circular Self-Test Path for FSMs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:4, pp:50-60 [Journal]
  145. Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
    RT-Level ITC'99 Benchmarks and First ATPG Results. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:3, pp:44-53 [Journal]
  146. Fulvio Corno, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero
    Automatic Test Program Generation: A Case Study. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:2, pp:102-109 [Journal]
  147. Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    The General Product Machine: a New Model for Symbolic FSM Traversal. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1998, v:12, n:3, pp:267-289 [Journal]
  148. Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
    Evolutionary Simulation-Based Validation. [Citation Graph (0, 0)][DBLP]
    International Journal on Artificial Intelligence Tools, 2004, v:13, n:4, pp:897-916 [Journal]
  149. Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero
    Efficient Techniques for Automatic Verification-Oriented Test Set Optimization. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2006, v:34, n:1, pp:93-109 [Journal]
  150. Matteo Sonza Reorda, Massimo Violante
    Efficient analysis of single event transients. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2004, v:50, n:5, pp:239-246 [Journal]
  151. Alfredo Benso, Maurizio Rebaudengo, Matteo Sonza Reorda
    Fault Injection for Embedded Microprocessor-based Systems. [Citation Graph (0, 0)][DBLP]
    J. UCS, 1999, v:5, n:10, pp:693-711 [Journal]
  152. G. P. Balboni, Gianpiero Cabodi, Silvano Gai, Matteo Sonza Reorda
    A Parallel System for Test Pattern Generation. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1993, v:19, n:2, pp:177-185 [Journal]
  153. Gianpiero Cabodi, Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda
    TPDL: Extended Temporal Profile Description Language. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 1991, v:21, n:4, pp:355-374 [Journal]
  154. Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante
    A New Hybrid Fault Detection Technique for Systems-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:2, pp:185-198 [Journal]
  155. Fulvio Corno, Uwe Gläser, Paolo Prinetto, Matteo Sonza Reorda, Heinrich Theodor Vierhaus, Massimo Violante
    SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:191-202 [Journal]
  156. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:991-1000 [Journal]
  157. Maurizio Rebaudengo, Matteo Sonza Reorda
    GALLO: a genetic algorithm for floorplan area optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:943-951 [Journal]
  158. Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    EXFI: a low-cost fault injection system for embedded microprocessor-based boards. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:4, pp:626-634 [Journal]
  159. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero
    Initializability analysis of synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:2, pp:249-264 [Journal]
  160. Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda
    Interactive presentation: An enhanced technique for the automatic generation of effective diagnosis-oriented test programs for processor. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1158-1163 [Conf]
  161. Salvatore Pontarelli, Luca Sterpone, Gian-Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante
    Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:194-196 [Conf]
  162. Paolo Bernardi, Leticia Maria Veiras Bolzani, Matteo Sonza Reorda
    A Hybrid Approach to Fault Detection and Correction in SoCs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:107-112 [Conf]
  163. Leticia Maria Veiras Bolzani, E. Sanchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero
    An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:265-270 [Conf]
  164. Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena
    Fault Injection-based Reliability Evaluation of SoPCs. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:75-82 [Conf]
  165. Paolo Bernardi, Michelangelo Grosso, E. Sanchez, Matteo Sonza Reorda
    On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:179-184 [Conf]
  166. Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Carro, Matteo Sonza Reorda
    On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  167. Paolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda
    Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  168. Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    New techniques for efficiently assessing reliability of SOCs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:1, pp:53-61 [Journal]
  169. Luca Sterpone, Matteo Sonza Reorda, Massimo Violante, Fernanda Lima Kastensmidt, Luigi Carro
    Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2007, v:23, n:1, pp:47-54 [Journal]

  170. On the Generation of Functional Test Programs for the Cache Replacement Logic. [Citation Graph (, )][DBLP]


  171. An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers. [Citation Graph (, )][DBLP]


  172. Hybrid symbolic-explicit techniques for the graph coloring problem. [Citation Graph (, )][DBLP]


  173. New static compaction techniques of test sequences for sequential circuits. [Citation Graph (, )][DBLP]


  174. A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs. [Citation Graph (, )][DBLP]


  175. A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips. [Citation Graph (, )][DBLP]


  176. An efficient fault simulation technique for transition faults in non-scan sequential circuits. [Citation Graph (, )][DBLP]


  177. An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs. [Citation Graph (, )][DBLP]


  178. Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs. [Citation Graph (, )][DBLP]


  179. An Exact and Efficient Critical Path Tracing Algorithm. [Citation Graph (, )][DBLP]


  180. An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains. [Citation Graph (, )][DBLP]


  181. Safety Evaluation of NanoFabrics. [Citation Graph (, )][DBLP]


  182. Optimization of Self Checking FIR filters by means of Fault Injection Analysis. [Citation Graph (, )][DBLP]


  183. An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs. [Citation Graph (, )][DBLP]


  184. An experimental analysis of the effectiveness of the circular self-test path technique. [Citation Graph (, )][DBLP]


  185. Diagnosis oriented test pattern generation. [Citation Graph (, )][DBLP]


  186. Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors. [Citation Graph (, )][DBLP]


  187. A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs. [Citation Graph (, )][DBLP]


  188. Exploiting embedded FPGA in on-line software-based test strategies for microprocessor cores. [Citation Graph (, )][DBLP]


  189. Evaluating Alpha-induced soft errors in embedded microprocessors. [Citation Graph (, )][DBLP]


  190. Automotive Microcontroller End-of-Line Test via Software-Based Methodologies. [Citation Graph (, )][DBLP]


  191. On Automatic Test Block Generation for Peripheral Testing in SoCs via Dynamic FSMs Extraction. [Citation Graph (, )][DBLP]


  192. A software-based methodology for the generation of peripheral test sets based on high-level descriptions. [Citation Graph (, )][DBLP]


  193. An optimized hybrid approach to provide fault detection and correction in SoCs. [Citation Graph (, )][DBLP]


  194. Design validation of multithreaded architectures using concurrent threads evolution. [Citation Graph (, )][DBLP]


  195. A parallel system for test pattern generation. [Citation Graph (, )][DBLP]


  196. A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions. [Citation Graph (, )][DBLP]


  197. An adaptive tester architecture for volume diagnosis. [Citation Graph (, )][DBLP]


  198. A software-based self-test methodology for system peripherals. [Citation Graph (, )][DBLP]


  199. Automatic Functional Stress Pattern Generation for SoC Reliability Characterization. [Citation Graph (, )][DBLP]


  200. Test Program Generation for Communication Peripherals in Processor-Based SoC Devices. [Citation Graph (, )][DBLP]


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