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Paolo Prinetto: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Silvia Chiusano, Fulvio Corno, Paolo Prinetto
    A Test Pattern Generation Algorithm Exploiting Behavioral Information. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:480-485 [Conf]
  2. Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    Guaranteeing Testability in Re-encoding for Low Power. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:30-35 [Conf]
  3. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    Memory Read Faults: Taxonomy and Automatic Test Generation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:157-163 [Conf]
  4. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    Specification and Design of a New Memory Fault Simulator. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:92-97 [Conf]
  5. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero
    A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:56-61 [Conf]
  6. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, Luca Tagliaferri
    Control-Flow Checking via Regular Expressions. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:299-303 [Conf]
  7. Fabrizio Bertuccelli, Franco Bigongiari, Andrea S. Brogna, Giorgio Di Natale, Paolo Prinetto, Roberto Saletti
    Exhaustive Test of Several Dependable Memory Architectures Designed by GRAAL Tool. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:32-37 [Conf]
  8. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:68-73 [Conf]
  9. Paolo Camurati, M. Gilli, Paolo Prinetto, Matteo Sonza Reorda
    The Use of Model Checking in ATPG for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:86-95 [Conf]
  10. Mario Baldi, Fulvio Corno, Maurizio Rebaudengo, Paolo Prinetto, Matteo Sonza Reorda, Giovanni Squillero
    Simulation-based verification of network protocols performance. [Citation Graph (0, 0)][DBLP]
    CHARME, 1997, pp:236-251 [Conf]
  11. Paolo Camurati, Fulvio Corno, Paolo Prinetto
    A Methodology for System-Level Design for Verifiability. [Citation Graph (0, 0)][DBLP]
    CHARME, 1993, pp:80-91 [Conf]
  12. Paolo Camurati, Fulvio Corno, Paolo Prinetto
    Exploiting Symbolic Traversal Techniques for Efficient Process Algebra Manipulation. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:31-44 [Conf]
  13. Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Silvano Gai, Paolo Prinetto, Matteo Sonza Reorda
    A New Model for Improving symbolic Product Machine Traversal. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:614-619 [Conf]
  14. Andrea Baldini, Alfredo Benso, Paolo Prinetto, Sergio Mo, Andrea Taddei
    Beyond UML to an End-of-Line Functional Test Engine. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:499-505 [Conf]
  15. Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    Automatic march tests generations for static linked faults in SRAMs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1258-1263 [Conf]
  16. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    SEU effect analysis in an open-source router via a distributed fault injection environment. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:219-225 [Conf]
  17. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    An Optimal Algorithm for the Automatic Generation of March Tests. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:938-943 [Conf]
  18. Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich
    Optimal Hardware Pattern Generation for Functional BIST. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:292-297 [Conf]
  19. Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Hans-Joachim Wunderlich
    On applying the set covering model to reseeding. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:156-161 [Conf]
  20. Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante
    Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:670-0 [Conf]
  21. Elizabeth M. Rudnick, Roberto Vietti, Akilah Ellis, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:570-576 [Conf]
  22. Yervant Zorian, Paolo Prinetto, João Paulo Teixeira, Isabel C. Teixeira, Carlos Eduardo Pereira, O. P. Dias, Jorge Semião, Peter Muhmenthaler, W. Radermacher
    Embedded tutorial: TRP: integrating embedded test and ATE. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:34-37 [Conf]
  23. Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:157-158 [Conf]
  24. Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    Automatic March Tests Generation for Multi-Port SRAMs. [Citation Graph (0, 0)][DBLP]
    DELTA, 2006, pp:385-392 [Conf]
  25. Marie-Lise Flottes, Yves Bertrand, L. Balado, E. Lupon, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, N. Pricopi, Hans-Joachim Wunderlich
    Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:135-139 [Conf]
  26. Michel Renovell, Penelope Faure, Paolo Prinetto, Yervant Zorian
    Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:297-301 [Conf]
  27. Andrea Baldini, Alfredo Benso, Silvia Chiusano, Paolo Prinetto
    'BOND': An Interposition Agents Based Fault Injector for Windows NT. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:387-395 [Conf]
  28. Alfredo Benso, Silvia Chiusano, Paolo Prinetto, P. Simonotti, G. Ugo
    Self-Repairing in a Micro-Programmed Processor for Dependable Applications. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:231-239 [Conf]
  29. Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Jaan Raik, Raimund Ubar
    Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:212-217 [Conf]
  30. Alfredo Benso, Silvia Chiusano, Paolo Prinetto, Luca Tagliaferri
    A C/C++ Source-to-Source Compiler for Dependable Applications. [Citation Graph (0, 0)][DBLP]
    DSN, 2000, pp:71-0 [Conf]
  31. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Maurizio Damiani, Leonardo Impagliazzo, G. Sartore
    On-line Testing of an Off-the-shelf Microprocessor Board for Safety-critical Applications. [Citation Graph (0, 0)][DBLP]
    EDCC, 1996, pp:190-202 [Conf]
  32. Paolo Camurati, Fulvio Corno, Paolo Prinetto, C. Bayol, B. Soulas
    System-Level Modeling and Verification: a Comprehensive Design Methodology. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:636-640 [Conf]
  33. Gianpiero Cabodi, Paolo Camurati, Paolo Prinetto
    Experiences in Prolog-Based DFT Rule Checking. [Citation Graph (0, 0)][DBLP]
    FJCC, 1986, pp:909-914 [Conf]
  34. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    A Parallel Genetic Algorithm for Automatic Generation of Test Sequences for Digital Circuits. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1996, pp:454-459 [Conf]
  35. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva
    A PVM tool for automatic test generation on parallel and distributed systems. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1995, pp:39-44 [Conf]
  36. Alfredo Benso, Stefano Di Carlo, Silvia Chiusano, Paolo Prinetto, Fabio Ricciato, Monica Lobetti Bodoni, Maurizio Spadari
    On Integrating a Proprietary and a Commercial Architecture for Optimal BIST Performances in SoCs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:539-540 [Conf]
  37. Alfredo Benso, Stefano Martinetto, Paolo Prinetto, Riccardo Mariani
    An SEU Injection Tool to Evaluate DSP-Based Architectures for Space Applications. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:537-538 [Conf]
  38. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero
    A new Approach for Initialization Sequences Computation for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:381-386 [Conf]
  39. S. Chuisano, Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    Exploiting Symbolic Techniques within Genetic Algorithms for Power Optimization. [Citation Graph (0, 0)][DBLP]
    ICTAI, 1997, pp:133-0 [Conf]
  40. Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    A Genetic Algorithm for Automatic Generation of Test Logic for Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ICTAI, 1996, pp:10-16 [Conf]
  41. Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva
    GATTO: An Intelligent Tool for Automatic Test Pattern Generation for Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ICTAI, 1994, pp:411-417 [Conf]
  42. Dominique Borrione, Paolo Prinetto
    Zero-Defect Designs, Why and How: Formal Verification vs. Automated Synthesis. [Citation Graph (0, 0)][DBLP]
    IFIP Congress, 1989, pp:233-240 [Conf]
  43. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    A Watchdog Processor to Detect Data and Control Flow Errors. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:144-148 [Conf]
  44. Alfredo Benso, Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni
    A Family of Self-Repair SRAM Cores. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2000, pp:214-218 [Conf]
  45. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, I. Solcia, Luca Tagliaferri
    FAUST: FAUlt-injection Script-based Tool. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:160- [Conf]
  46. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Luca Tagliaferri, Paolo Prinetto
    Validation of a Software Dependability Tool via Fault Injection Experiments. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:3-8 [Conf]
  47. Alfredo Benso, Silvia Chiusano, Paolo Prinetto
    A COTS Wrapping Toolkit for Fault Tolerant Applications under Windows NT. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2000, pp:9-16 [Conf]
  48. Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto
    Automated Synthesis of SEU Tolerant Architectures from OO Descriptions. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:26-31 [Conf]
  49. Andrea Baldini, Alfredo Benso, Paolo Prinetto, Sergio Mo, Andrea Taddei
    Towards a unified test process: from UML to end-of-line functional test. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:600-608 [Conf]
  50. Andrea Baldini, Alfredo Benso, Paolo Prinetto, Sergio Mo, Andrea Taddei
    Efficient Design of System Test: A Layered Architecture. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:930-939 [Conf]
  51. Stefano Barbagallo, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    Testing a Switching Memory in a Telcommunication System. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:947-956 [Conf]
  52. Alfredo Benso, Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Fabio Ricciato, Maurizio Spadari, Yervant Zorian
    HD/sup 2/BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:892-901 [Conf]
  53. Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian
    HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1038-1044 [Conf]
  54. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    Static Analysis of SEU Effects on Software Applications. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:500-508 [Conf]
  55. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni
    A programmable BIST architecture for clusters of multiple-port SRAMs. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:557-566 [Conf]
  56. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, Luca Tagliaferri
    Data Critically Estimation In Software Applications. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:802-810 [Conf]
  57. Alfredo Benso, Silvia Chiusano, Paolo Prinetto
    A software development kit for dependable applications in embedded systems. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:170-178 [Conf]
  58. Alfredo Benso, Silvia Chiusano, Paolo Prinetto, Simone Giovannetti, Riccardo Mariani, Silvano Motto
    Testing an MCM for high-energy physics experiments: a case study. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:38-46 [Conf]
  59. Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    A fault injection environment for microprocessor-based boards. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:768-773 [Conf]
  60. Monica Lobetti Bodoni, Alessio Pricco, Alfredo Benso, Silvia Chiusano, Paolo Prinetto
    An on-line BISTed SRAM IP core. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:993-1000 [Conf]
  61. Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    Sequential Circuit Diagnosis Based on Formal Verification Techniques. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:187-196 [Conf]
  62. Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Franco Bigongiari
    GRAAL: a tool for highly dependable SRAMs generation. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:250-257 [Conf]
  63. Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich
    Non-intrusive BIST for systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:644-651 [Conf]
  64. Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    Making the Circular Self-Test Path Technique Effective for Real Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:949-957 [Conf]
  65. Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    Testability Analysis and ATPG on Behavioral RT-Level VHDL. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:753-759 [Conf]
  66. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    Comparing Topological, Symbolic and GA-based ATPGs: An Experimental Approach. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:39-47 [Conf]
  67. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    Partial Scan Flip Flop Selection for Simulation-Based Sequential ATPGs. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:558-564 [Conf]
  68. Liviu Miclea, Enyedi Szilárd, Gavril Toderean, Alfredo Benso, Paolo Prinetto
    Agent Based DBIST/DBISR And Its Web/Wireless Management. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:952-960 [Conf]
  69. Liviu Miclea, Enyedi Szilárd, Gavril Toderean, Alfredo Benso, Paolo Prinetto
    Towards Microagent based DBIST/DBISR. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:867-874 [Conf]
  70. Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:240-249 [Conf]
  71. Yves Bertrand, Marie-Lise Flottes, L. Balado, Joan Figueras, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, N. Pricopi, Hans-Joachim Wunderlich, J.-P. Van der Heyden
    Test Engineering Education in Europe: the EuNICE-Test Project. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:85-86 [Conf]
  72. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    Exploiting Competing Subpopulations for Automatic Generation of Test Sequences for Digital Cicuits. [Citation Graph (0, 0)][DBLP]
    PPSN, 1996, pp:792-800 [Conf]
  73. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    SAARA: a simulated annealing algorithm for test pattern generation for digital circuits. [Citation Graph (0, 0)][DBLP]
    SAC, 1997, pp:228-232 [Conf]
  74. Andrea S. Brogna, Franco Bigongiari, Silvia Chiusano, Paolo Prinetto, Roberto Saletti
    Designing and Testing High Dependable Memories for Aerospace Applications. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:221-0 [Conf]
  75. J. Abraham, P. Frankl, Christian Landrault, Meryem Marzouki, Paolo Prinetto, Chantal Robach, Pascale Thévenod-Fosse
    Hardware Test: Can We Learn from Software Testing? [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:320-321 [Conf]
  76. Stefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    Scan insertion criteria for low design impact. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:26-31 [Conf]
  77. Silvia Chiusano, Fulvio Corno, Paolo Prinetto
    RT-level TPG Exploiting High-Level Synthesis Information. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:341-353 [Conf]
  78. Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    Cellular automata for deterministic sequential test pattern generation. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:60-67 [Conf]
  79. Fulvio Corno, Nicola Gaudenzi, Paolo Prinetto, Matteo Sonza Reorda
    On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:424-429 [Conf]
  80. Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Uwe Gläser, Heinrich Theodor Vierhaus
    Improving topological ATPG with symbolic techniques. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:338-343 [Conf]
  81. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    A Test Pattern Generation Methodology for Low-Power Consumption. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:453-459 [Conf]
  82. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva
    A portable ATPG tool for parallel and distributed systems. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:29-34 [Conf]
  83. Mark D. Hill, Jean-Luc Gaudiot, Mary W. Hall, Joe Marks, Paolo Prinetto, Donna Baglio
    A Wiki for discussing and promoting best practices in research. [Citation Graph (0, 0)][DBLP]
    Commun. ACM, 2006, v:49, n:9, pp:63-64 [Journal]
  84. Paolo Camurati, Paolo Prinetto
    Formal Verification of Hardware Correctness: Introduction and Survey of Current Research. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1988, v:21, n:7, pp:8-19 [Journal]
  85. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    Online Self-Repair of FIR Filters. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:3, pp:50-57 [Journal]
  86. Alfredo Benso, Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni
    Online and Offline BIST in IP-Core Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:5, pp:92-99 [Journal]
  87. Alfredo Benso, Silvia Chiusano, Paolo Prinetto
    DFT and BIST of a Multichip Module for High-Energy Physics Experiments. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:3, pp:94-105 [Journal]
  88. Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Yervant Zorian
    A Hierarchical Infrastructure for SoC Test Management. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:4, pp:32-39 [Journal]
  89. Stefano Barbagallo, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    Integrating Online and Offline Testing of a Switching Memory. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:1, pp:63-70 [Journal]
  90. Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda, Stefano Barbagallo, Andrea Burri, Davide Medina
    Industrial BIST of Embedded RAMs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:3, pp:86-95 [Journal]
  91. Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    Circular Self-Test Path for FSMs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:4, pp:50-60 [Journal]
  92. Paolo Prinetto, Alfredo Benso
    Test Technology TC Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:2, pp:164-165 [Journal]
  93. Andrea Baldini, Alfredo Benso, Paolo Prinetto
    A Dependable Autonomic Computing Environment for Self-Testing of Complex Heterogeneous Systems. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2005, v:116, n:, pp:47-57 [Journal]
  94. Andrea Baldini, Paolo Prinetto, Giovanni Denaro, Mauro Pezzè
    Design for Testability for Highly Reconfigurable Component-Based Systems. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2003, v:82, n:6, pp:- [Journal]
  95. Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    The General Product Machine: a New Model for Symbolic FSM Traversal. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1998, v:12, n:3, pp:267-289 [Journal]
  96. Alfredo Benso, Silvia Chiusano, Paolo Prinetto
    A Self-Repairing Execution Unit for Microprogrammed Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2001, v:21, n:5, pp:16-22 [Journal]
  97. Gianpiero Cabodi, Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda
    TPDL: Extended Temporal Profile Description Language. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 1991, v:21, n:4, pp:355-374 [Journal]
  98. Marco Mezzalama, Paolo Prinetto
    A Machine-independent Approach to Microprogram Synthesis. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 1982, v:12, n:10, pp:985-1010 [Journal]
  99. Andrea Baldini, Alfredo Benso, Paolo Prinetto
    System-level functional testing from UML specifications in end-of-production industrial environments. [Citation Graph (0, 0)][DBLP]
    STTT, 2005, v:7, n:4, pp:326-340 [Journal]
  100. Marco Mezzalama, Paolo Prinetto
    A Hierarchical Description Model for Microcode. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:5, pp:478-487 [Journal]
  101. Fabio Somenzi, Silvano Gai, Marco Mezzalama, Paolo Prinetto
    Testing Strategy and Technique for Macro-Based Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:1, pp:85-90 [Journal]
  102. Paolo Camurati, P. Gianoglio, R. Gianoglio, Paolo Prinetto
    ESTA: an expert system for DFT rule verification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:11, pp:1172-1180 [Journal]
  103. Fulvio Corno, Uwe Gläser, Paolo Prinetto, Matteo Sonza Reorda, Heinrich Theodor Vierhaus, Massimo Violante
    SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:191-202 [Journal]
  104. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:991-1000 [Journal]
  105. Fabio Somenzi, Silvano Gai, Marco Mezzalama, Paolo Prinetto
    PART: Programmable Array Testing Based on a Partitioning Algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:2, pp:142-149 [Journal]
  106. Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    EXFI: a low-cost fault injection system for embedded microprocessor-based boards. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:4, pp:626-634 [Journal]
  107. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero
    Initializability analysis of synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:2, pp:249-264 [Journal]
  108. Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale
    Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:205-206 [Conf]
  109. Mohammad Hosseinabady, Pejman Lotfi-Kamran, Giorgio Di Natale, Stefano Di Carlo, Alfredo Benso, Paolo Prinetto
    Single-Event Upset Analysis and Protection in High Speed Circuits. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:29-34 [Conf]
  110. Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    A 22n March Test for Realistic Static Linked Faults in SRAMs. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:49-54 [Conf]

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  112. Hybrid symbolic-explicit techniques for the graph coloring problem. [Citation Graph (, )][DBLP]


  113. New static compaction techniques of test sequences for sequential circuits. [Citation Graph (, )][DBLP]


  114. A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs. [Citation Graph (, )][DBLP]


  115. Test exploration and validation using transaction level models. [Citation Graph (, )][DBLP]


  116. System Level Testing via TLM 2.0 Debug Transport Interface. [Citation Graph (, )][DBLP]


  117. A process algebra interpretation of a verification oriented overlanguage of VHDL. [Citation Graph (, )][DBLP]


  118. An experimental analysis of the effectiveness of the circular self-test path technique. [Citation Graph (, )][DBLP]


  119. Diagnosis oriented test pattern generation. [Citation Graph (, )][DBLP]


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  123. An Avatar-Based Italian Sign Language Visualization System. [Citation Graph (, )][DBLP]


  124. Are IEEE-1500-Compliant Cores Really Compliant to the Standard?. [Citation Graph (, )][DBLP]


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