The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Ramesh Harjani: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Wooyoung Choi, Ramesh Harjani, Bapiraju Vinnakota
    Optimal test-set generation for parametric fault detection in switched capacitor filters. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:72-77 [Conf]
  2. Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley
    A Prototype Framework for Knowledge-Based Analog Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:42-49 [Conf]
  3. Ramesh Harjani, Bapiraju Vinnakota
    Digital Aetection of Analog Parametric Faults in SC Filters. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:772-777 [Conf]
  4. Bapiraju Vinnakota, Ramesh Harjani, Nicholas J. Stessman
    System-Level Design for Test of Fully Differential Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:450-454 [Conf]
  5. Jianfeng Shao, Ramesh Harjani
    Macromodeling of analog circuits for hierarchical circuit design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:656-663 [Conf]
  6. Brian A. Blow, Ramesh Harjani, Dennis L. Polla, Takashi Tamagawa
    A Dual Frequency Range Integrated Circuit Accelerometer Using Capacitive and Piezoelectric Sensing Techniques. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1120-1123 [Conf]
  7. Shubha Bommalingaiahnapallya, Ramesh Harjani
    Low power implementation of an n-tone Sigma Delta converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:461-464 [Conf]
  8. Shubha Bommalingaiahnapallya, Ramesh Harjani
    Process tolerant design of N-tone Sigma-Delta converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4630-4633 [Conf]
  9. Andrew Cable, Ramesh Harjani
    A 6-Bit 50MHz Current-Subtracting Two Step Flash Converter. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:465-468 [Conf]
  10. Byunghoo Jung, Shubha Bommalingaiahnapallya, Ramesh Harjani
    Power optimized LC VCO and mixer co-design. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4393-4396 [Conf]
  11. Byunghoo Jung, Anand Gopinath, Ramesh Harjani
    A novel noise optimization design technique for radio frequency low noise amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:209-212 [Conf]
  12. Byunghoo Jung, Ramesh Harjani
    A wide tuning range VCO using capacitive source degeneration. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:145-148 [Conf]
  13. Byunghoo Jung, Yi-Hung Tseng, Jackson Harvey, Ramesh Harjani
    Pulse generator design for UWB IR communication systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4381-4384 [Conf]
  14. Deepa S. Parthasarathy, Ramesh Harjani
    Novel integratable notch filter implementation for 100 dB image rejection. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:473-476 [Conf]
  15. Rongtai Wang, Ramesh Harjani
    Suppression of acoustic oscillations in hearing aids using minimum phase techniques. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:818-821 [Conf]
  16. Feng Wang, Ramesh Harjani
    Dynamic Amplifiers: Settling, Slewing and Power Issues. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:319-322 [Conf]
  17. Wooyoung Choi, Ramesh Harjani, Bapiraju Vinnakota
    Non-ideal amplifier effects on the accuracy of analog-to-digital capacitor ratio converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:552-555 [Conf]
  18. R. Balczewski, Ramesh Harjani
    Capacitive voltage multipliers: a high efficiency method to generate multiple on-chip supply voltages. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:508-511 [Conf]
  19. Jackson Harvey, Ramesh Harjani
    Analysis and gain design of an integrated quadrature mixer with improved noise and image rejection. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:786-789 [Conf]
  20. Jonghae Kim, Ramesh Harjani
    An ISM band CMOS integrated transceiver design for wireless telemetry system. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:694-697 [Conf]
  21. Kavita Nair, Ramesh Harjani
    A telemetry and interface circuit for piezoelectric sensors. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 1999, pp:152-155 [Conf]
  22. Liang Dai, Ramesh Harjani
    Analysis and design of low-phase-noise ring oscillators. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:289-294 [Conf]
  23. Ramesh Harjani
    Analog Circuits for Wireless Communications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:7- [Conf]
  24. Ramesh Harjani, Jackson Harvey
    Tutorial: CMOS Analog Circuits for Wireless Communications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:18- [Conf]
  25. Ramesh Harjani, Jackson Harvey, Robert Sainati
    Analog/RF Physical Layer Issues For UWB Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:941-0 [Conf]
  26. Jackson Harvey, Ramesh Harjani
    An Integrated Quadrature Mixer with Improved Image Rejection at Low Voltage. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:269-273 [Conf]
  27. Kavita Nair, Ramesh Harjani
    Compact, Ultra Low Power, Programmable Continuous-Time Filter Banks for Feedback Cancellation in Hearing Aid. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:55-60 [Conf]
  28. K. Roy, R. Roy, Ramesh Harjani, K. S. Murthy
    T5: Low-Power Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:4-0 [Conf]
  29. Sachin S. Sapatnekar, Jaijeet S. Roychowdhury, Ramesh Harjani
    High-Speed Interconnect Technology: On-Chip and Off-Chip. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:7-0 [Conf]
  30. Bapiraju Vinnakota, Ramesh Harjani
    The Design of Analog Self-Checking Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:67-70 [Conf]
  31. Bapiraju Vinnakota, Ramesh Harjani
    Mixed-Signal Design for Test. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:2- [Conf]
  32. Bapiraju Vinnakota, Ramesh Harjani, Wooyoung Choi
    Pseudoduplication - An ACOB Technique for Single-Ended Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:398-402 [Conf]
  33. Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley
    OASYS: a framework for analog circuit synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1247-1266 [Journal]
  34. Bapiraju Vinnakota, Ramesh Harjani
    DFT for digital detection of analog parametric faults in SC filters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:789-798 [Journal]
  35. Shubha Bommalingaiahnapallya, Kin-Joe Sham, Mahmoud Reza Ahmadi, Ramesh Harjani
    High-Speed Circuits for a Multi-Lane 12 Gbps CMOS PRBS Generator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3896-3899 [Conf]

Search in 0.003secs, Finished in 0.004secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002