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Bapiraju Vinnakota: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Wooyoung Choi, Ramesh Harjani, Bapiraju Vinnakota
    Optimal test-set generation for parametric fault detection in switched capacitor filters. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:72-77 [Conf]
  2. Ramesh Harjani, Bapiraju Vinnakota
    Digital Aetection of Analog Parametric Faults in SC Filters. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:772-777 [Conf]
  3. Wanli Jiang, Bapiraju Vinnakota
    IC Test Using the Energy Consumption Ratio. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:976-981 [Conf]
  4. Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota
    Combining dictionary coding and LFSR reseeding for test data compression. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:944-947 [Conf]
  5. Dechang Sun, Bapiraju Vinnakota, Wanli Jiang
    Fast State Verification. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:619-624 [Conf]
  6. Bapiraju Vinnakota, Jason Andrews
    Functional Test Generation for FSMs by Fault Extraction. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:712-715 [Conf]
  7. Bapiraju Vinnakota, Ramesh Harjani, Nicholas J. Stessman
    System-Level Design for Test of Fully Differential Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:450-454 [Conf]
  8. Bapiraju Vinnakota, Niraj K. Jha
    Design of Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    FTCS, 1991, pp:504-511 [Conf]
  9. Minesh B. Amin, Bapiraju Vinnakota
    Zamlog: a parallel algorithm for fault simulation based on Zambezi. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:509-512 [Conf]
  10. Seonki Kim, Bapiraju Vinnakota
    Fast Test Application Technique Without Fast Scan Clocks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:464-467 [Conf]
  11. Xiaoyun Sun, Seonki Kim, Bapiraju Vinnakota
    Crosstalk Fault Detection by Dynamic Idd. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:375-0 [Conf]
  12. Bapiraju Vinnakota
    Deep submicron defect detection with the energy consumption ratio. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:467-470 [Conf]
  13. Minesh B. Amin, Bapiraju Vinnakota
    Data parallel fault simulation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:610-615 [Conf]
  14. Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi
    A C-Testable Carry-Free Divider. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:206-213 [Conf]
  15. Amit K. Varshney, Bapiraju Vinnakota, Eric Skuldt, Brion L. Keller
    High Performance Parallel Fault Simulation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:308-313 [Conf]
  16. Bapiraju Vinnakota, Jason Andrews
    Repair of RAMs With Clustered Faults. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:582-585 [Conf]
  17. Wooyoung Choi, Ramesh Harjani, Bapiraju Vinnakota
    Non-ideal amplifier effects on the accuracy of analog-to-digital capacitor ratio converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:552-555 [Conf]
  18. Wanli Jiang, Bapiraju Vinnakota
    Statistical threshold formulation for dynamic I_dd test. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:57-66 [Conf]
  19. Seonki Kim, Sreejit Chakravarty, Bapiraju Vinnakota
    An analysis of the delay defect detection capability of the ECR test method. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:1060-1069 [Conf]
  20. Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota
    Test Vector Generation Based on Correlation Model for Ratio-Iddq. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:545-554 [Conf]
  21. Bapiraju Vinnakota, Wanli Jiang, Dechang Sun
    Process-tolerant test with energy consumption ratio. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:1027-1036 [Conf]
  22. Bapiraju Vinnakota, Ramesh Harjani
    The Design of Analog Self-Checking Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:67-70 [Conf]
  23. Bapiraju Vinnakota, Ramesh Harjani
    Mixed-Signal Design for Test. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:2- [Conf]
  24. Bapiraju Vinnakota, Ramesh Harjani, Wooyoung Choi
    Pseudoduplication - An ACOB Technique for Single-Ended Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:398-402 [Conf]
  25. Minesh B. Amin, Bapiraju Vinnakota
    ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:438-443 [Conf]
  26. Wanli Jiang, Bapiraju Vinnakota
    Defect-Oriented Test Scheduling. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:433-439 [Conf]
  27. Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota
    Development of Energy Consumption Ratio Test. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:279-286 [Conf]
  28. Xiaoyun Sun, Bapiraju Vinnakota
    Current Measurement for Dynamic Idd Test. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:117-123 [Conf]
  29. Bapiraju Vinnakota
    Monitoring power dissipation for fault detection. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:483-488 [Conf]
  30. Bapiraju Vinnakota, André Ivanov
    Biomedical ICs: What is Different about Testing those ICs? [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:329-332 [Conf]
  31. Bapiraju Vinnakota, Nicholas J. Stessman
    Reducing test application time in scan design schemes. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:367-373 [Conf]
  32. Bapiraju Vinnakota, V. V. Bapeswara Rao
    Enumeration of Binary Trees. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1994, v:51, n:3, pp:125-127 [Journal]
  33. Bapiraju Vinnakota
    Implementing Multiplication with Split Read-Only Memory. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:11, pp:1352-1356 [Journal]
  34. Bapiraju Vinnakota, Niraj K. Jha
    Diagnosability and Diagnosis of Algorithm-Based Fault-Tolerant Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:8, pp:924-937 [Journal]
  35. Bapiraju Vinnakota, V. V. Bapeswara Rao
    Generation of All Reed-Muller Expansions of a Switching Function. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:1, pp:122-124 [Journal]
  36. Wanli Jiang, Bapiraju Vinnakota
    IC test using the energy consumption ratio. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:129-141 [Journal]
  37. Wanli Jiang, Bapiraju Vinnakota
    Statistical threshold formulation for dynamic Idd test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:6, pp:694-705 [Journal]
  38. Bapiraju Vinnakota, Ramesh Harjani
    DFT for digital detection of analog parametric faults in SC filters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:789-798 [Journal]
  39. Bapiraju Vinnakota, Niraj K. Jha
    Synthesis of Algorithm-Based Fault-Tolerant Systems from Dependence Graphs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1993, v:4, n:8, pp:864-874 [Journal]
  40. Bapiraju Vinnakota, Niraj K. Jha
    Design of Algorithm-Based Fault-Tolerant Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1994, v:5, n:10, pp:1099-1106 [Journal]
  41. Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi
    A C-testable carry-free divider. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:472-488 [Journal]
  42. Bapiraju Vinnakota, Jason Andrews
    Fast fault translation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:122-133 [Journal]
  43. Minesh B. Amin, Bapiraju Vinnakota
    Data parallel fault simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:183-190 [Journal]
  44. Wanli Jiang, Bapiraju Vinnakota
    Defect-oriented test scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:3, pp:427-438 [Journal]

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