Search the dblp DataBase

Publications of Author

1. Ehsan Atoofian, Zainalabedin Navabi
   A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2003, pp:84-89 [Conf]
   
2. Kaveh Aasaraai, Amirali Baniasadi, Ehsan Atoofian
   Computational and storage power optimizations for the O-GEHL branch predictor. [Citation Graph (0, 0)][DBLP]
   Conf. Computing Frontiers, 2007, pp:105-112 [Conf]
   
3. Ehsan Atoofian, Amirali Baniasadi, Kaveh Aasaraai
   Speculative supplier identification for reducing power of interconnects in snoopy cache coherence protocols. [Citation Graph (0, 0)][DBLP]
   Conf. Computing Frontiers, 2007, pp:259-266 [Conf]
   
4. Ehsan Atoofian, Amirali Baniasadi
   Improving Energy-Efficiency by Bypassing Trivial Computations. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2005, pp:- [Conf]
   
5. Mohammad Alisafaee, Safar Hatami, Ehsan Atoofian, Zainalabedin Navabi, Ali Afzali-Kusha
   A low-power scan-path architecture. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2005, pp:5278-5281 [Conf]
   
6. Ehsan Atoofian, Zainalabedin Navabi
   A Low Power BIST Architecture for FPGA Look-Up Table Testing. [Citation Graph (0, 0)][DBLP]
   VLSI-SOC, 2003, pp:394-397 [Conf]
   
7. Ehsan Atoofian, Zainalabedin Navabi
   A Test Approach for Look-Up Table Based FPGAs. [Citation Graph (0, 0)][DBLP]
   J. Comput. Sci. Technol., 2006, v:21, n:1, pp:141-146 [Journal]
   
8. Ehsan Atoofian, Amirali Baniasadi
   A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2007, pp:1-8 [Conf]
   
9. Ehsan Atoofian, Amirali Baniasadi
   Speculative trivialization point advancing in high-performance processors. [Citation Graph (0, 0)][DBLP]
   Journal of Systems Architecture, 2007, v:53, n:9, pp:587-601 [Journal]
   
10. Ehsan Atoofian, Amirali Baniasadi, Kaveh Aasaraai
    Exploiting Speculation Cost Prediction in Power-Aware Applications. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2007, v:3, n:1, pp:43-53 [Journal]
    
11. 
    Adaptive Read Validation in Time-Based Software Transactional Memory. [Citation Graph (, )][DBLP]
    
    
12. 
    Exploiting program cyclic behavior to reduce memory latency in embedded processors. [Citation Graph (, )][DBLP]