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Prab Varma: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Bechir Ayari, Prab Varma
    Test Cycle Count Reduction in a Parallel Scan BIST Environment. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:21-26 [Conf]
  2. Sandeep Bhatia, Prab Varma
    Test Compaction in a Parallel Access Scan Environment. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:300-305 [Conf]
  3. S. B. Tan, K. Totton, Keith Baker, Prab Varma, R. Porter
    A Fast Signature Simulation Tool for Built-In Self-Testing Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:17-25 [Conf]
  4. Prab Varma
    System Chip Test Challenges, Are There Solutions Today? (Panel). [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:750-751 [Conf]
  5. Sandeep Bhatia, Tushar Gheewala, Prab Varma
    A Unifying Methodology for Intellectual Property and Custom Logic Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:639-648 [Conf]
  6. Prab Varma
    Design Verification Problems: Test To The Rescue?. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1292- [Conf]
  7. Prab Varma
    Scan DFT: Why More Can Cost Less. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:267- [Conf]
  8. Prab Varma
    On Path-Delay Testing in a Standard Scan Environment. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:164-173 [Conf]
  9. Prab Varma
    Optimizing Product Profitability - The Test Way. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:922- [Conf]
  10. Prab Varma
    System chip test: are we there yet? [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:1144- [Conf]
  11. Prab Varma, Anthony P. Ambler, Keith Baker
    An Analysis of the Economics of Self Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1984, pp:20-30 [Conf]
  12. Prab Varma, Sandeep Bhatia
    A structured test re-use methodology for core-based system chips. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:294-302 [Conf]
  13. Prab Varma, Tushar Gheewala
    Delay Testing Using a Matrix of Accessible Storage. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:243-252 [Conf]
  14. Magdy S. Abadir, Scott Davidson, Vijay Nagasamy, Dhiraj K. Pradhan, Prab Varma
    ATPG for Design Errors-Is It Possible? [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:283-285 [Conf]
  15. Sandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma
    Delay Fault Testing: How Robust are Our Models? [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:502-503 [Conf]
  16. Prab Varma
    Verification evolution or industrial revolution? [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:2, pp:168-0 [Journal]

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